PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 85

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
18
18.1
18.2
18.3
18.4
Reset timing and device status at reset
Power-up reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t
steady. During this period, the device loads internal configurations, clears some of the
registers and sets the Flash memory into operating mode. After the rising edge of Reset
(RESET), the PSD remains in the Reset mode for an additional period, t
memory access is allowed.
The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR, CNTL0) high, during Power On
Reset for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when V
Warm reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, t
The same t
Figure 33
I/O pin, register and PLD status at Reset
Table 34
Power-down mode. PLD outputs are always valid during warm reset, and they are valid in
Power On Reset once the internal PSD Configuration bits are loaded. This loading of PSD is
completed typically long before the V
the state of the outputs are determined by the PSDabel equations.
Reset of Flash memory erase and program cycles (on the
PSD834Fx)
A Reset (RESET) also resets the internal Flash memory state machine. During a Flash
memory program or erase cycle, Reset (RESET) terminates the cycle and returns the Flash
memory to the Read mode within a period of t
shows the I/O pin, register and PLD status during Power On Reset, warm reset and
NLNH
shows the timing of the Power-up and warm reset.
OPR
.
period is needed before the device is operational after warm reset.
Doc ID 7833 Rev 7
CC
ramps up to operating level. Once the PLD is active,
NLNH-A
CC
Reset timing and device status at reset
is below V
.
LKO
.
NLNH-PO
OPR
, before the first
after V
85/128
CC
is