PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 115
PSD813F2-A-70J
Manufacturer Part Number
PSD813F2-A-70J
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2-A-70J.pdf
(128 pages)
Specifications of PSD813F2-A-70J
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PLCC
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
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PSD8XXFX
Table 69.
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For program or erase PLD only.
Table 70.
1. t
Table 71.
1. t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Symbol
Symbol
ISCCF
ISCCH
ISCCL
ISCCFP
ISCCHP
ISCCLP
ISCPSU
ISCPH
ISCPCO
ISCPZV
ISCPVZ
LVDV
CLWH
LVDV
CLWH
CLCL
CLCL
is the period of CLKIN (PD1).
is the period of CLKIN (PD1).
Clock (TCK, PC1) frequency (except for
PLD)
Clock (TCK, PC1) high time (except for
PLD)
Clock (TCK, PC1) low time (except for
PLD)
Clock (TCK, PC1) frequency (PLD only)
Clock (TCK, PC1) high time (PLD only)
Clock (TCK, PC1) low time (PLD only)
ISC port setup time
ISC port hold up time
ISC port clock to output
ISC port high-Impedance to valid Output
ISC port valid Output to high-Impedance
ALE access time from Power-down
Maximum delay from APD Enable to
Internal PDN valid signal
ALE access time from Power-down
Maximum Delay from APD Enable to
Internal PDN valid Signal
ISC timing (3 V devices)
Power-down timing (5 V devices)
Power-down timing (3 V devices)
Parameter
Parameter
Parameter
Doc ID 7833 Rev 7
Using CLKIN
Using CLKIN
Conditions
Conditions
Conditions
(PD1)
(PD1)
(1)
(1)
(1)
(2)
(2)
(2)
Min Max Min Max Min Max
240
240
Min Max Min Max Min Max
Min Max Min Max Min Max
40
40
12
5
-12
-70
-12
145
12
30
30
30
80
2
15 * t
15 * t
240
240
45
45
13
5
-15
-90
-15
CLCL
CLCL
150
10
36
36
36
90
2
AC/DC parameters
(1)
(1)
240
240
51
51
15
5
-20
-15
-20
150
200
40
40
40
9
2
115/128
MHz
MHz
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
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