ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 83

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. HcControl register: bit allocation . . . . . . . . . . .37
Table 11. HcControl register: bit description . . . . . . . . . .38
Table 12. HcCommandStatus register: bit allocation . . . .39
Table 13. HcCommandStatus register: bit description . . .39
Table 14. HcInteruptStatus register: bit allocation . . . . . .40
Table 15. HcInterruptStatus register: bit description . . . .40
Table 16. HcInterruptEnable register: bit allocation . . . . .41
Table 17. HcInterruptEnable register: bit description . . . .41
Table 18. HcInterruptDisable register: bit allocation . . . .42
Table 19. HcInterruptDisable register: bit description . . .42
Table 20. HcFmInterval register: bit allocation . . . . . . . .43
Table 21. HcFmInterval register: bit description . . . . . . .44
Table 22. HcFmRemaining register: bit allocation . . . . . .44
Table 23. HcFmRemaining register: bit description . . . . .45
Table 24. HcFmNumber register: bit allocation . . . . . . . .45
Table 25. HcFmNumber register: bit description . . . . . . .45
Table 26. HcLSThreshold register: bit allocation . . . . . . .46
Table 27. HcLSThreshold register: bit description . . . . . .46
Table 28. HcRhDescriptorA register: bit description . . . .47
Table 29. HcRhDescriptorA register: bit description . . . .48
Table 30. HcRhDescriptorB register: bit allocation . . . . .49
Table 31. HcRhDescriptorB register: bit description . . . .49
Table 32. HcRhStatus register: bit allocation . . . . . . . . . .50
Table 33. HcRhStatus register: bit description . . . . . . . . .51
Table 34. HcRhPortStatus[1:2] register: bit allocation . . .52
Table 35. HcRshPortStatus[1:2] register: bit description .52
Table 36. HcHardwareConfiguration register: bit
Table 37. HcHardwareConfiguration register: bit
Table 38. HcDMAConfiguration register: bit allocation . .57
Table 39. HcDMAConfiguration register: bit description .57
Table 40. HcTransferCounter register: bit allocation . . . .58
Table 41. HcTransferCounter register: bit description . . .58
Table 42. HcmPInterrupt register: bit allocation . . . . . . . .58
Table 43. HcmPInterrupt register: bit description . . . . . .59
Table 44. HcmPInterruptEnable register: bit allocation . .60
Table 45. HcmPInterruptEnable register: bit description .60
Table 46. HcChipID register: bit allocation . . . . . . . . . . .61
Table 47. HcChipID register: bit description . . . . . . . . . .61
Table 48. HcScratch register: bit allocation . . . . . . . . . . .61
Table 49. HcScratch register: bit description . . . . . . . . . .61
Table 50. HcSoftwareReset register: bit allocation . . . . .61
Table 51. HcSoftwareReset register: bit description . . . .62
Table 52. HcITLBufferLength register: bit allocation . . . .62
ISP1160-01_7
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description LQFP64 . . . . . . . . . . . . . . . . . . .4
I/O port addressing . . . . . . . . . . . . . . . . . . . . .10
Proprietary Transfer Descriptor (PTD): bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Proprietary Transfer Descriptor (PTD): bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Run results of the C program example . . . . . .27
HC registers summary . . . . . . . . . . . . . . . . . . .35
HcRevision register: bit allocation . . . . . . . . . .36
HcRevision register: bit description . . . . . . . . .37
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Rev. 07 — 29 September 2009
Table 53. HcITLBufferLength register: bit description . . . 62
Table 54. HcATLBufferLength register: bit allocation . . . 63
Table 55. HcATLBufferLength register: bit description . . 63
Table 56. HcBufferStatus register: bit allocation . . . . . . . 63
Table 57. HcBufferStatus register: bit description . . . . . . 63
Table 58. HcReadBackITL0Length register: bit
Table 59. HcReadBackITL0Length register: bit
Table 60. HcReadBackITL1Length register: bit
Table 61. HcReadBackITL1Length register: bit
Table 62. HcITLBufferPort register: bit allocation . . . . . . 65
Table 63. HcITLBufferPort register: bit description . . . . . 65
Table 64. HcATLBufferPort register: bit allocation . . . . . 66
Table 65. HcATLBufferPort register: bit description . . . . 66
Table 66. Absolute maximum ratings . . . . . . . . . . . . . . . 69
Table 67. Recommended operating conditions . . . . . . . . 69
Table 68. Static characteristics; supply pins . . . . . . . . . . 70
Table 69. Static characteristics: digital pins . . . . . . . . . . 70
Table 70. Static characteristics: analog I/O pins D+ and
Table 71. Dynamic characteristics . . . . . . . . . . . . . . . . . 72
Table 72. Dynamic characteristics: analog I/O pins D+ and
Table 73. Dynamic characteristics: programmed interface
Table 74. Dynamic characteristics: single-cycle DMA
Table 75. Dynamic characteristics: burst mode DMA
Table 76. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 82
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
D− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
D− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Embedded USB host controller
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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