ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 57

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 38.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDMAConfiguration register: bit allocation
10.4.2 HcDMAConfiguration register (R/W: 21H/A1H)
10.4.3 HcTransferCounter register (R/W: 22H/A2H)
reserved
R/W
R/W
15
0
7
0
Code (Hex): 21 — read
Code (Hex): A1 — write
Table 39.
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the
number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However, for
this counter to be read into the DMA counter, the HCD must set bit 2 (DMACounterSelect)
of the HcDMAConfiguration register. The counter value for ATL must not be greater than
1000H, and for ITL it must not be greater than 800H. When the byte count of the data
Bit
15 to 7
6 to 5
4
3
2
1
0
R/W
R/W
14
0
6
0
BurstLen[1:0]
Symbol
-
BurstLen[1:0]
DMAEnable
-
DMACounterS
elect
ITL_ATL_
DataSelect
DMARead
WriteSelect
HcDMAConfiguration register: bit description
R/W
R/W
13
0
5
0
Rev. 07 — 29 September 2009
Description
reserved
00 — single-cycle burst DMA
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
0 — DMA is terminated
1 — DMA is enabled
This bit will be reset to logic 0 when DMA transfer is completed.
reserved
0 — DMA counter not used. External EOT must be used
1 — enables the DMA counter for DMA transfer. HcTransferCounter
register must be filled with non-zero values for DREQ to be raised
after bit DMA Enable is set.
0 — ITL buffer RAM selected for ITL data
1 — ATL buffer RAM selected for ATL data
0 — read from the HC FIFO buffer RAM
1 — write to the HC FIFO buffer RAM
Enable
DMA
R/W
R/W
12
0
4
0
reserved
reserved
R/W
R/W
11
0
3
0
Counter
Select
Embedded USB host controller
DMA
R/W
R/W
10
0
2
0
DataSelect
ISP1160/01
ITL_ATL_
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
0
1
0
WriteSelect
DMARead
R/W
R/W
8
0
0
0
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