ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 10

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1160-01_7
Product data sheet
8.3.1 I/O port addressing
8.3.2 Register access phases
8.3 Control registers access by PIO mode
Table 3
address should include the chip select signal CS_N and the address line A0. However,
the direction of access of I/O ports is controlled by the RD_N and WR_N signals. When
RD_N is LOW, the microprocessor reads data from the ISP1160/01’s data port. When
WR_N is LOW, the microprocessor writes a command to the command port, or writes data
to the data port.
Table 3.
Figure 5
control registers.
The ISP1160/01’s register structure is a command-data register pair structure. A complete
register access cycle comprises a command phase followed by a data phase. The
command (also known as the index of a register) points the ISP1160/01 to the next
register to be accessed. A command is 8 bits long. On a microprocessor’s 16-bit data bus,
a command occupies the lower byte, with the upper byte filled with zeros.
Figure 6
microprocessor writes a command code to the command port, and then reads from or
writes the data word to the data port. Take the example of a microprocessor attempting to
read the ISP1160/01’s ID, which is saved in the HC’s HcChipID register (index 27H, read
only). The 16-bit register access cycle is therefore:
Port
0
1
1. The microprocessor writes the command code of 27H (0027H in 16-bit width) to the
2. The microprocessor reads the data word of the chip’s ID from the HC data port.
Fig 5.
HC command port
shows the ISP1160/01’s I/O port addressing. Complete decoding of the I/O port
illustrates how an external microprocessor accesses the ISP1160/01’s internal
shows a complete 16-bit register access cycle for the ISP1160/01. The
When A0 = 0, microprocessor accesses the data port.
When A0 = 1, microprocessor accesses the command port.
Access to internal control registers.
CS_N
0
0
I/O port addressing
Host bus I/F
A0
0
1
Rev. 07 — 29 September 2009
A0
CMD/DATA
Access
R/W
W
SWITCH
1
0
Data bus width
(bits)
16
16
command port
data port
Control registers
. .
.
Embedded USB host controller
Description
HC data port
HC command port
Command register
Commands
004aaa075
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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