ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 84

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

12. DC DMA transfer
ISP1161A1_5
Product data sheet
12.1 Selecting an endpoint for DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to another in
a computer system, without intervention of the Central Processor Unit (CPU). Many
different implementations of DMA exist. The ISP1161A1 DC supports two methods:
The ISP1161A1’s DC supports DMA transfer for all 14 configurable endpoints (see
Table
operation of the ISP1161A1’s DC can be interleaved with normal I/O mode access to
other endpoints.
The following features are supported:
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the
DcDMAConfiguration register, as shown in
is automatically set by bit EPDIR in the associated ECR, to match the selected endpoint
type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK2 automatically selects the endpoint specified in the
DcDMAConfiguration register, regardless of the current endpoint used for I/O mode
access.
Table 70.
Endpoint
identifier
1
2
3
4
5
6
7
8
9
10
•
•
•
•
•
•
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the Intel
8237 DMA controller and has separate address spaces for memory and I/O
DACK-only mode: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O.
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions, short/empty
packet
Programmable signal levels on pins DREQ2 and EOT.
66). Only one endpoint at a time can be selected for DMA transfer. The DMA
Endpoint selection for DMA transfer
EPIDX[3:0]
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Rev. 05 — 29 September 2009
Transfer direction
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
Table
USB single-chip host and device controller
70. The transfer direction (read or write)
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
84 of 137