ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 28

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Table 20.
CD00222684
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hardware Configuration Register: bit allocation
reserved
DAKOLY
R/W
R/W
15
0
7
0
Transaction — write/read 2 bytes
Table 21.
Bit
15
14
13
12
11 to 8
7
6
5
4
3
DRQPOL
EXTPUL
R/W
R/W
14
0
6
1
Hardware Configuration Register: bit description
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
DAKOLY
DRQPOL
DAKPOL
EOTPOL
WKUPCS
NOLAZY
DAKPOL
R/W
R/W
13
1
5
0
Rev. 05 — 25 August 2010
Description
reserved
A logic 1 indicates that an external 1.5 kΩ pull-up resistor is used
on pin D+ and that SoftConnect is not used. Bus reset value:
unchanged.
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz ± 50 %) during ‘suspend’ state. A logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP in
the Mode Register. Bus reset value: unchanged.
A logic 1 indicates that the internal clocks are always running, even
during ‘suspend’ state. A logic 0 switches off the internal oscillator
and PLL, when they are not needed. During ‘suspend’ state this bit
must be made logic 0 to meet the suspend current requirements.
The clock is stopped after a delay of approximately 2 ms, following
the setting of bit GOSUSP in the Mode Register. Bus reset value:
unchanged.
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in MHz is
given by
3 MHz to 48 MHz (N = 0 to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237
compatible DMA mode. Bus reset value: unchanged.
Selects DREQ signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Selects DACK signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Selects EOT signal polarity (0 = active LOW, 1 = active HIGH). Bus
reset value: unchanged.
A logic 1 enables remote wake-up via a LOW level on input CS (For
wake-up on CS to work, V
unchanged.
CLKRUN
EOTPOL
R/W
R/W
12
0
4
0
48
⁄
(
N
WKUPCS
+
R/W
R/W
1
11
)
0
3
0
. The clock frequency range is
Full-speed USB peripheral controller
BUS
PWROFF
must be present). Bus reset value:
R/W
R/W
10
0
2
0
CLKDIV[3:0]
INTLVL
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
ISP1181B
9
1
1
0
INTPOL
R/W
R/W
8
1
0
0
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