ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 18

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

CD00222684
Product data sheet
10.4.1.1 External EOT
10.4.1.2 DMA Counter Register
10.4.1 Bulk endpoints
10.4 End-Of-Transfer conditions
In DACK-only mode the ISP1181B uses the DACK signal as data strobe. Input signals RD
and WR are ignored. This mode is used in CPU systems that have a single address space
for memory and I/O access. Such systems have no separate MEMW and MEMR signals:
the RD and WR signals are also used as memory data strobes.
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DMA Configuration Register, see
When reading from an OUT endpoint, an external EOT will stop the DMA operation and
clear any remaining data in the current FIFO. For a double- buffered endpoint the other
(inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data packet
in the FIFO (even if it is smaller than the maximum packet size) will be sent to the USB
host at the next IN token.
An EOT from the DMA Counter Register is enabled by setting bit CNTREN in the DMA
Configuration Register. The ISP1181B has a 16-bit DMA Counter Register, which
specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the
internal DMA counter is loaded with the value from the DMA Counter Register. When the
internal counter completes the transfer as programmed in the DMA counter, an EOT
condition is generated and the DMA operation stops.
Fig 5.
•
•
•
•
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
ISP1181B in DACK-only DMA mode.
DATA1 to DATA15
ISP1181B
Rev. 05 — 25 August 2010
DREQ
DACK
AD0,
RAM
DREQ
DACK
RD
WR
CONTROLLER
Full-speed USB peripheral controller
DMA
HLDA
HRQ
Table
HRQ
HLDA
© ST-ERICSSON 2010. All rights reserved.
ISP1181B
CPU
004aaa138
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