M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 37

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.15 Interrupt Status Register 3
R e v 1 . 0 1
(1) EPB_EMP_OVR (Buffer Empty/Size Over Interrupt) Bits (b6~b0)
b15
15~7
Interrupt Status Register 3 (INT_STATUS3)
6~0
0
0
-
b
These bits indicate that the received data size exceeds the maximum packet size or that the buffers of the
endpoints 0 to 6 are empty.
The conditions for this bit to be cleared to “0” in all bits are as follows:
2 0 0 4 . 1 1 . 0 1
Note:
Reserved. Set it to “0”.
EPB_EMP_OVR
Buffer Empty/Size Over Interrupt
14
0
0
-
Endpoint 0
Endpoint 1~6
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
13
0
0
-
When set to control write transfer (ISEL bit = “0”)
When set to control read transfer (ISEL bit = “1”)
When set to OUT buffer (EPi_DIR bit = “0”)
When set to IN buffer (EPi_DIR bit = “1”)
The condition for this bit to be set to “1” is as follows:
In this case, the EP0_PID bits are set to STALL response.
Further the CTRT bit sets to “1” if the SERR bit is set to “1”.
This bit is set to “1” when size-over is detected, irrespective of the EP0_PID bit setting.
The condition for this bit to be set to “1” is as follows:
The condition for this bit to be set to “1” is as follows:
The EPi_PID bits are set to STALL response.
This bit isn’t set to “1” at isochronous transfer.
This bit is set to “1” when size-over is detected, irrespective of the EP0_PID bit setting.
The condition for this bit to be set to “1” is as follows:
•
p a g e 3 7 o f 1 2 2
•
•
•
•
•
12
0
0
-
Bit name
Writes “0” to this bit.
(Size-over detection).
When the IVAL bit of the EP0_FIFO Control Register changes from “1” to “0”.
When transmit data exist in the buffer for EP0_FIFO and “1” is written to the BCLR bit.
Receives packet data with size exceeding the one set by the EPi_MXPS bits
(Size-over detection).
When the data of SIE side buffer are all transmitted with the data not written to the CPU
side buffer (Buffer empty).
Receives packet data with size exceeding the one set by the EP0 Packet Size Register
11
0
0
-
10
0
0
-
9
0
0
-
0 :
1 :
0 :
1 :
b6 corresponds to EP6, ---b1 corresponds to EP1 and b0
corresponds to EP0.
Read
Write
8
0
0
-
No occurrence of interrupt
Occurrence of interrupt
Clear interrupt
Invalid (Ignored when written)
7
0
0
-
6
0
0
-
Function
5
0
0
-
4
0
0
-
EPB_EMP_OVR
3
0
0
-
2
0
0
-
<H/W reset : H'0000>
<S/W reset : H'0000>
<Address : H’1E>
<USB bus reset : ->
1
0
0
-
R
0
b0
0
0
-
W
0