FDC37B782-NS Standard Microsystems (SMSC), FDC37B782-NS Datasheet - Page 15

• Manufacturer Part Number: FDC37B782-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B782-NS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
The address map, shown below in Table 4, shows
the addresses of the different blocks of the Super
I/O immediately after power up.
addresses of the FDC, serial and parallel ports can
be moved via the configuration registers. Some
addresses are used to access more than one
register.
Base+(0-5) and +(7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
70,71, Base, Base+(1)
60, 64
Base + (0-17h)
Base + (0-1)
Note 1: Refer to the configuration register descriptions for setting the base address.
ADDRESS
TABLE 3 - SUPER I/O BLOCK ADDRESSES
The base
Floppy Disk
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
Serial Port Com 1
Serial Port Com 2
RTC
KYBD
ACPI, PME, SMI
Configuration
BLOCK NAME
14
HOST PROCESSOR INTERFACE
The host processor communicates with the
FDC37B78x through a series of read/write
registers. The port addresses for these registers
are shown in Table 4.
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide. All host
interface output buffers are capable of sinking a
minimum of 12 mA.
LOGICAL
DEVICE
0
3
4
5
6
7
A
IR Support
Consumer IR
NOTES
Register access is