FDC37B782-NS Standard Microsystems (SMSC), FDC37B782-NS Datasheet - Page 148

• Manufacturer Part Number: FDC37B782-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B782-NS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

REGISTERS
The following registers can be accessed when in
configuration
Registers B0-B3, B8 and F4, and when not in
configuration they can be accessed through the
Index and Data Register. All soft power
management configuration registers are battery
backed up and are reset on Vbat POR.
Soft Power Enable Registers
S
(Configuration Register B0, Logical Device 8)
This register contains the enable bits for the
wake-up function of the nPowerOn bit.
enabled, these bits allow their corresponding
function to turn on power to the system.
S
(Configuration Register B1, Logical Device 8)
This register contains additional enable bits for
the wake-up function of the nPowerOn bit. When
enabled, these bits allow their corresponding
function to turn on power to the system. It also
contains OFF_EN: After power up, this bit
defaults to 1, i.e., enabled. This bit allows the
software to enable or disable the button control
of power off.
Soft Power Status Registers
Soft Power Status Register 1
(Configuration Register B2, Logical Device 8)
This register contains the status for the wake-up
events.
wakeup event occurs, whether or not it is
enabled as a wakeup function by setting the
corresponding bit in Soft Power Enable Register
1. However, only the enabled wakeup functions
will turn on power to the system.
Soft Power Status Register 2
(Configuration Register B3, Logical Device 8)
This register contains additional status for the
wake-up events. Note: The status bit gets set if
the wakeup event occurs, whether or not it is
enabled as a wakeup function by setting the
corresponding bit in Soft Power Enable Register
OFT
OFT
P
P
OWER
OWER
Note: The status bit gets set if the
E
E
mode
NABLE
NABLE
R
R
at
EGISTER
EGISTER
Logical
1
2
Device
When
8,
150
2. However, only the enabled wakeup functions
will turn on power to the system.
Soft Power Control Registers
WDT_CTRL
(Configuration Register F4, Logical Device 8)
This register is used for soft power management
and watchdog timer control. Bits [7:5] are for soft
power
Stop_Cnt.
Delay 2 Time Set Register
(Configuration Register B8, Logical Device 8)
This register is used to set Delay 2 to value from
500msec to 32sec. The default value is
500msec.
The power button has an override event as
required by the ACPI specification. If the user
presses the power button for more than four
seconds while the system is in the working state,
a hardware event is generated and the system
will transition to the off state. There are status
bits and enable bits associated with this feature
in the PM1_BLK registers.
section.
This override event utilizes power button logic to
determine that the power button (Button_In) has
been pressed for more that four seconds. The
override enable/disable bit, PWRBTNOR_EN,
allows this override function to be turned on/off.
If enabled, this override event will result in setting
the override status bit, PWRBTNOR_STS (to be
cleared by writing a 1 to its bit position - writing a
0 has no effect), clearing the regular button
status bit, PWRBTN_STS, and generating an
event to be routed into the soft power
management logic to turn off the system. The
override status bit alerts the system upon power-
up that an override event was used to power
down the system, and will be used to properly
power-up the system.
Figure 11 shows the soft power management
logic with the override timer path from the button
input. The override timer counts while the button
is held (in the present implementation this would
be when the button input is high) and is cleared
management:
SPOFF,
See the ACPI
Restart_Cnt,