MCIMX27MOP4A Freescale, MCIMX27MOP4A Datasheet - Page 92

• Manufacturer Part Number: MCIMX27MOP4A
• Manufacturer: Freescale

Specifications of MCIMX27MOP4A

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
4.3.12
All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising
edge or falling edge according to corresponding assertion/negation control fields. Address always begins
related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according
to control register configuration. Output data begins related to BCLK rising edge except in muxed mode
where both rising and falling edge may be used according to control register configuration. Input data,
ECB and DTACK all captured according to BCLK rising edge time.
WEIM module, and
92
Wireless External Interface Module (WEIM)
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when the SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will
be same as that of Tx Data, for example, during the AC97 mode of
operation.
Table 50
lists the timing parameters.
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
NOTE
Figure 53
shows the timing of the
Freescale Semiconductor