MCIMX27MOP4A Freescale, MCIMX27MOP4A Datasheet - Page 7

• Manufacturer Part Number: MCIMX27MOP4A
• Manufacturer: Freescale

Specifications of MCIMX27MOP4A

• Lead Free Status / RoHS Status: Compliant

Block Mnemonic
Freescale Semiconductor
PCMCIA
JTAGC
MSHC
LCDC
PWM
M3IF
MAX
NFC
KPP
PLL
I
IIM
2
C
Crossbar Switch
JTAG Controller
Communication
IC Identification
Multi-layer AHB
Host Controller
Liquid Crystal
Memory Stick
Memory Card
Block Name
Multi-Master
NAND Flash
International
Keypad Port
Pulse-Width
Phase Lock
Association
Computer
Modulator
Controller
Controller
Interface
Personal
Memory
Inter IC
Module
Display
Loop
Table 2. Digital and Analog Modules (continued)
Reset Control
Connectivity
Connectivity
Connectivity
Bus Control
Functional
Multimedia
Grouping
Peripheral
Peripheral
Peripheral
Peripheral
Clock and
Interface
Interface
Interface
Interface
Security
External
Memory
External
Memory
External
Memory
Debug
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Timer
The I
and other external devices. Data rates of up to 100 Kbits/s are
supported.
The IIM provides an interface for reading—and in some cases,
programming, and overriding identification and control
information stored in on-chip fuse elements.
Contact your Freescale Semiconductor sales office or
distributor for additional information on SCC, RTIC, IIM,
SAHARA2
The JTAGC provides debug access to the ARM926 core,
built-in self-test (BIST), and boundary scan test control.
The KPP is used for key pad matrix scanning or as a general
purpose I/O. This peripheral simplifies the software task of
scanning a keypad matrix.
The LCDC provides display data for external gray-scale or
color LCD panels.
The M3IF controls memory accesses from one or more
masters through different port interfaces to different external
memory controllers ESDCTL/MDDRC, PCMCIA, NFC, and
WEIM.
The ARM926EJ-S processor’s instruction and data buses and
all alternate bus master interfaces arbitrate for resources via a
6 × 3 MAX. There are six fully functional master ports (M0–M5)
and three fully functional slave ports (S0–S2). The MAX is
uni-directional. All master and slave ports are AHB-Lite
compliant.
The MSHC is placed in between the AIPI and the customer
memory stick to support data transfer from the i.MX27 device
to the customer memory stick.
Note: The i.MX27L does not support the MSHC feature
The NFC is a submodule of EMI. The NFC implements the
interface to standard NAND Flash memory devices.
The PCMCIA host adapter module provides the control logic
for PCMCIA socket interfaces, and requires some additional
external analog power switching logic and buffering.
The two DPLLs provide clock generation in digital and mixed
analog/digital chips designed for wireless communication and
other applications.
The PWM has a 16-bit counter and is optimized to generate
sound from stored sample audio images. It can also generate
tones.
2
C provides serial interface to control the sensor interface
Brief Description
Functional Description and Application Information
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