AT88SA102S-TH-T Atmel, AT88SA102S-TH-T Datasheet - Page 2

• Manufacturer Part Number: AT88SA102S-TH-T
• Manufacturer: Atmel

Specifications of AT88SA102S-TH-T

• Lead Free Status / RoHS Status: Supplier Unconfirmed

1.1.
1.2.
2
The CryptoAuthentication family uses a standard challenge response protocol to simplify programming. The system
generates a random number challenge and sends it to the CryptoAuthentication chip. The chip hashes that with a 256
bit key using the SHA-256 algorithm to generate a keyed 256 bit response which is sent back to the system.
The chip includes 128 single bit one time programmable fuses that can be used for personalization, status or
consumption logging. Atmel programs 40 of these bits prior to the chip leaving the factory, leaving 88 for user
purposes. Refer to Section 1.3 for more information.
Note:
Usage
There are many different ways in which CryptoAuthentication can add an authentication capability to a system. For
more information, refer to the “CryptoAuthentication Usage Examples” Applications Note.
In general, however, all these security models usually employ one of two general key management strategies:
• Fixed challenge response number pair stored in the host. In this case, the host sends its particular challenge and
• Host computes the response that should be provided for a particular client against a random challenge and/or
Memory Resources
Fuse
ROM
ROM MfrID
ROM SN
RevNum
AT88SA102S
only an authentic CryptoAuthentication can generate the correct response. Since no secret is stored on the host,
there is no security cost on the host. Depending on the particulars of the system, each host may have a different
challenge response pair and/or each client may have the same key.
include the client ID# in the calculation. In this case, the host needs to have the capability to securely store the secret
from which diversified response will be computed. One way to do this is to use a CryptoAuthentication host chip.
Since each client is unique, the host can maintain a dynamic black list of clients that have been found to be
fraudulent.
The chip implements a failsafe internal watchdog timer that forces it into a very low power mode after a certain
time interval regardless of any command execution or IO transfers that may be happening at the time the timer
expires. System programming must take this into consideration. Refer to Section 4.5 for more details.
Block of 128 fuse bits that can be written through the 1 wire interface. Fuse[1] and Fuse[87] have
special meanings, refer to Section 1.3 for more details. Fuse[88:95] are part of the manufacturing ID
value fixed by Atmel. Fuse[96:127] are part of the serial number programmed by Atmel which is
guaranteed to be unique. See Section 1.4 for more details on the Manufacturing ID and Serial
Number.
Metal mask programmed memory. Unrestricted reads are permitted on the first 64 bits of this array.
The physical ROM will be larger and will contain other information that cannot be read.
2 bytes of ROM that specifies part of the manufacturing ID code. This value is assigned by Atmel and
is always the same for all chips of a particular model number. For the AT88SA102S, this value is
0x23 01. (Appears on the bus: 0x01 23) ROM MfrID can be read by accessing ROM bytes 0 & 1 of
Address 0.
2 bytes of ROM that can be used to identify chips among others on the wafer. These bits reduce the
number of fuses necessary to construct a unique serial number. The ROM SN is read by accessing
ROM bytes 2 & 3 of Address 0. ROM SN can always be read by the system and is optionally
included in the message digested by the MAC command.
4 bytes of ROM that are used by Atmel to identify the model mask and/or design revision of the
AT88SA102S chip. These bytes can be freely read as the four bytes returned ROM address 1,
however system code should not depend on this value as it may change from time to time.
8584D–SMEM–5/10