W9751G6JB-3 Winbond, W9751G6JB-3 Datasheet - Page 47

• Manufacturer Part Number: W9751G6JB-3
• Manufacturer: Winbond
• Type: DDR2 SDRAMr

Specifications of W9751G6JB-3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 150mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Notes:
1. All voltages are referenced to V
2. Tests for AC timing, I
3. AC timing reference load:
4. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min)
5. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ
6. This is an optional feature. For detailed information, please refer to “operating temperature condition” section 9.2 in this data
7. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the
8. A minimum of two clocks (2 *nCK) is required irrespective of operating frequency.
9. tWTR is at least two clocks (2 * nCK) independent of operation frequency.
10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for
Logic levels
V
VDDQ
REF
DUT
levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is
disabled for all measurements that are not ODT-specific.
have been satisfied.
can be executed.
sheet.
valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value
tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and
VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to
1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667,
DDR2-800 and DDR2-1066 (page 55).
CLK
CLK
levels
Figure 16
Figure 17
DQS
DQS
DQ
Output
–
–
DD
AC timing reference load
Differential input waveform timing
t
Timing
reference
point
, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage
t
IS(ref)
IS(base)
SS
.
t
IH(base)
25Ω
t
IH(ref)
VTT = VDDQ/2
t
IS(ref)
t
IS(base)
–
- 47 -
tIS and tIH
t
IH(base)
t
IH(ref)
Publication Release Date: Jun. 18, 2010
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
W9751G6JB
max
max
min
min
Revision A03