W9751G6JB-3 Winbond, W9751G6JB-3 Datasheet - Page 24

• Manufacturer Part Number: W9751G6JB-3
• Manufacturer: Winbond
• Type: DDR2 SDRAMr

Specifications of W9751G6JB-3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 150mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

7.4.2
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or
from memory locations (read cycle). The parameters that define how the burst mode will operate are
burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8
bit burst mode, full interleave address ordering is supported, however, sequential address ordering is
nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].
The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless
burst read or write operations are supported.
Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is
prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to
two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms
refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10)
DQS/DQS
DQS/DQS
CLK /CLK
CLK/CLK
CMD
Burst mode operation
CMD
DQ
DQ
-1
-1
where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4
where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4
Figure 14 – Example 1: Read followed by a write to the same bank,
Figure 15 – Example 2: Read followed by a write to the same bank,
A-Bank
Active
A-Bank
Active
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
0
0
A-Bank
≥ t
Read
1
≥ t
RCD
1
RCD
AL=2
2
2
A-Bank
AL=0
Read
3
3
RL=AL+CL=5
RL=AL+CL=3
CL=3
4
4
A-Bank
- 24 -
CL=3
Write
5
5
6
6
Dout0
Dout0 Dout1 Dout2 Dout3
Dout1 Dout2 Dout3
A-Bank
Write
WL=RL-1=4
7
7
Publication Release Date: Jun. 18, 2010
WL=RL-1=2
8
8
Din0
Din0
9
9
Din1
Din1
W9751G6JB
10
Din2
Din2
10
Din3
Din3
11
11
Revision A03
12
12