K4D263238KVC50 Samsung Semiconductor, K4D263238KVC50 Datasheet - Page 8

• Manufacturer Part Number: K4D263238KVC50
• Manufacturer: Samsung Semiconductor
• Type: FPMr

Specifications of K4D263238KVC50

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 60mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

K4D263238K
MODE REGISTER SET(MRS)
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
addressing mode uses A
used for DLL reset. A
for various burst length, addressing modes and CAS latencies.
* RFU(Reserved for future use)
RFU
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
BA
should stay "0" during MRS
cycle.
MRS Cycle
BA
Command
0
1
1
CK, CK
0
BA
0
0
*1: MRS can be issued only at all banks precharge state.
*2: Minimum
EMRS
A
MRS
0
n
~ A
DLL
~ A
A
11
A
0
1
11
NOP
8
0
7,
and BA
A
8
RFU
0
A
3
DLL Reset
, BA
t
, CAS latency(read latency from column address) uses A
10
RP
Yes
No
Precharge
All Banks
is required to issue MRS command.
0
0
, BA
and BA
A
9
1
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
1
DLL
must be set to low for normal MRS operation. Refer to the table for specific codes
CAS Latency
A
NOP
8
A
0
0
0
0
1
1
1
1
Test Mode
6
A
2
0
1
7
TM
A
0
0
1
1
0
0
1
1
t
A
RP
5
7
NOP
Normal
A
0
1
0
1
0
1
0
1
mode
Test
4
3
A
6
CAS Latency
- 8/19 -
Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MRS
A
3
5
4
t
A
MRD
NOP
4
Burst Length
=2 t
A
0
0
0
0
1
1
1
1
5
Burst Type
2
CK
BT
A
A
0
1
3
Command
3
A
0
0
1
1
0
0
1
1
4
Any
1
~ A
128M GDDR SDRAM
Sequential
Interleave
A
6
A
0
1
0
1
0
1
0
1
2
6
Burst Length
0
. A
Type
Rev. 1.2 October 2007
7
NOP
Sequential
Full page
is used for test mode. A
A
Reserve
Reserve
Reserve
Reserve
1
7
2
4
8
Burst Type
A
0
NOP
8
Address Bus
Interleave
Register
Reserve
Reserve
Reserve
Reserve
Reserve
Mode
2
4
8
0
~ A
8
2
is
,