K4D263238KVC50 Samsung Semiconductor, K4D263238KVC50 Datasheet
K4D263238KVC50
Specifications of K4D263238KVC50
Related parts for K4D263238KVC50
K4D263238KVC50 Summary of contents
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... Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Revision 1.2 October 2007 - 1/19 - 128M GDDR SDRAM Rev. 1.2 October 2007 ...
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... K4D263238K Revision History Revision Month Year 1.0 January 2007 1.1 July 2007 - Release revision 1.0 SPEC - Corrected Package Outline - Revised comment about voltage of power up sequence - Revised ICC2P current to 20mA - 2/19 - 128M GDDR SDRAM History Rev. 1.2 October 2007 ...
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... K4D263238K 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 2.5V ± 5% power supply for device operation • 2.5V ± 5% power supply for I/O interface • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs - ...
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... VSS VSS A10 VDD VDD BA1 A2 A11 DDQ V SSQ NC - 4/19 - 128M GDDR SDRAM DQ29 DQ28 VSSQ DM3 DQ30 VDDQ NC VDDQ VSSQ VSSQ VSSQ DQ26 VSSQ VSS VDD VDDQ VSS VSSQ VDDQ DQ15 Thermal VSS VSSQ VDDQ DQ13 Thermal VSS VSSQ NC DM1 ...
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... REF *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply V 128M GDDR SDRAM Function The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ ′ ...
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... Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS WE DMi - 6/19 - 128M GDDR SDRAM LWE LDMi 64 32 x32 DQi Data Strobe DLL CK,CK LDMi Rev. 1.2 October 2007 ...
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... K4D263238K FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or with - Apply VDDQ before or with - The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power voltage ramps are without any slope reversal ...
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... The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A ...
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... DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 A5 A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register ...
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... DD of the transmitting device and to track variations in the DC level of the same. Peak to DDQ of the receiving device. REF ≤ acceptable. For all other pins that are not under test 10/19 - 128M GDDR SDRAM Value Unit -0.5 ~ 3.6 V -1.0 ~ 3.6 V -0.5 ~ 3.6 V °C -55 ~ +150 1 ...
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... CKE ≤ 0.2V =0V =2.5V DDQ Symbol Min V V +0.35 IH REF 0 0.5*V -0.2 IX DDQ of the transmitting device and must track variations in the DC level of the same DDQ - 11/19 - 128M GDDR SDRAM Version Unit -40 -50 189 170 153 134 mA 402 344 mA 159 135 5 65° ...
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... IN1 ) C 1 IN2 C IN3 ~ OUT C IN4 Symbol and and V C SSQ pins are connected in chip. DDQ pins are connected in chip. SSQ - 12/19 - 128M GDDR SDRAM 65°C) A Value Unit V DDQ 1.5 V 1.0 V/ns -0.35 V REF V V REF See Fig.1 V =0.5*V tt DDQ R =50Ω ...
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... Da1 Da2 - 13/19 - 128M GDDR SDRAM -50 Min Max 5.0 10 0.45 0.55 0.45 0.55 -0.7 +0.7 -0.7 +0.7 - +0.45 0.9 1.1 0.4 0.6 0.8 1 0.25 - 0.4 ...
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... X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL3, BL2 CK DQS DQ COMMAND READA 128M GDDR SDRAM tHP tDQSQ(max) tQH tDQSQ(max) Da0 Da1 - 14/ Rev. 1.2 October 2007 ...
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... Exit self refresh to read command Power down exit time Refresh interval time Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM 2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP 3. The number of clock of tWR_A is fixed. It can’t be changed by tCK 4 ...
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... Normal Write Burst (@ BL= BAa BAa BAb PRECH ACTIVEA ACTIVEB tRP tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 16/19 - 128M GDDR SDRAM BAa BAb Ca Cb Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 WRITEA WRITEB Rev. 1.2 October 2007 ...
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... K4D263238K PACKAGE DIMENSIONS (144-Ball FBGA) 0.10 Max 0.45 ± 0.05 0.35 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0 ± 0.05 0.40 Max <Bottom View> - 17/19 - 128M GDDR SDRAM 12.0 A1 INDEX MARK 0.8 0.40 Unit : mm Rev. 1.2 October 2007 ...
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... Voltage(V) 1 1.5 - 18/19 - 128M GDDR SDRAM Pullup Current(mA) 30% Min 30% Max -1.1495 -2.898 -3.6575 -6.888 -5.795 -10.794 -8.208 -14.49 -10.716 -18.186 -13.072 -21.798 -15.238 -25.116 -17 ...
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... Voltage(V) - 19/19 - 128M GDDR SDRAM Pullup Current(mA) 60% Max 30% Min 30% Max 0 0 5.88 1.539 4.872 11.676 5.32 9.576 17.304 8.74 14.238 22.848 12.046 18.732 28.224 15 ...