MT46H32M16LFCK-6 L Micron Technology Inc, MT46H32M16LFCK-6 L Datasheet - Page 23

• Manufacturer Part Number: MT46H32M16LFCK-6 L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M16LFCK-6 L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 105mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 9: I
Notes 1–5 apply to all parameters/conditions in this table; V
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Parameter/Condition
Operating 1 bank active precharge current:
t
dress inputs are switching every 2 clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle CKE =
HIGH; CS = HIGH;
switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle, CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Active power-down standby current: 1 bank active, CKE = LOW;
CS = HIGH;
ing; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac-
tive, CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS =
HIGH;
Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active,
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4; CL = 3;
(MIN); Continuous READ bursts; I
switching every 2 clock cycles; 50% data changing each burst
Operating burst write: One bank active; BL = 4;
Continuous WRITE bursts; Address inputs are switching; 50% da-
ta changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data bus
inputs are stable
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
CK (MIN); CKE is HIGH; CS is HIGH between valid commands; Ad-
t
CK =
DD
t
CK =
t
CK (MIN); Address and control inputs are switching;
Specifications and Conditions (x32)
t
t
t
CK (MIN); Address and control inputs are switch-
CK =
CK =
t
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
OUT
= 0mA; Address inputs are
t
RC =
t
CK =
t
t
t
RFC = 110ns
RFC =
RC (MIN);
t
CK =
t
CK (MIN);
t
REFI
t
CK
DD
23
t
CK =
/V
Electrical Specifications – I
DDQ
512Mb: x16, x32 Mobile LPDDR SDRAM
Symbol
= 1.70–1.95V
I
I
I
I
I
I
I
I
I
I
I
DD2NS
DD3NS
DD2PS
DD3PS
DD4W
I
DD2N
DD3N
DD4R
I
DD5A
I
DD2P
DD3P
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD0
DD5
DD8
300
300
125
125
105
70
15
15
-5
8
3
2
8
3
300
300
120
120
105
-54
65
15
15
8
3
2
8
3
Max
10
300
300
115
115
100
© 2004 Micron Technology, Inc. All rights reserved.
60
15
15
-6
8
3
2
8
3
DD
-75
300
300
100
100
100
50
12
15
8
3
2
8
3
Parameters
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6