S71NS128NB0BJWRN0 Spansion Inc., S71NS128NB0BJWRN0 Datasheet - Page 8
S71NS128NB0BJWRN0
Manufacturer Part Number
S71NS128NB0BJWRN0
Description
Manufacturer
Spansion Inc.
Datasheet
1.S71NS128NB0BJWRN0.pdf
(14 pages)
Specifications of S71NS128NB0BJWRN0
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
4.2
8
4.2.1
Connection Diagrams
pSRAM Based Pinout, 56-Ball, VFBGA
Notes
1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
2. CLK and WAIT signals are Flash only for the S71NS064NA0-RT, while on that MCP, the CRE signal won't exist.
S71NS128NC0
S71NS128NB0
S71NS128NA0
S71NS064NB0
S71NS064NA0
S71NS064N80
MCP
NC
K3
NC
A1
R-WAIT
A/DQ15 A/DQ14
F-RDY/
V
V
C3
NC
D3
E3
G3
H3
NC
CCQ
F3
SS
D a t a
A/DQ7
RFU
A21
A16
RFU
D4
G4
H4
C4
E4
F4
Figure 4.1 pSRAM Based Pinout, 56-Ball, VFBGA
Flash-Only Addresses
A/DQ6
V
V
A20
D5
E5
G5
F5
SSQ
SS
S h e e t
S71NS-N MCP Products
A22-A21
A22-A20
A21-A20
A21-A19
A/DQ13 A/DQ12
56-ball Fine-Pitch Ball Grid Array
A/DQ5
AVD#
A22
A21
(Top View, Balls Facing Down)
CLK
D6
E6
G6
F6
A/DQ4
R-CE#
R-LB#
DNU
V
H7
C7
D7
E7
F7
G7
CC
( A d v a n c e
A/DQ11 A/DQ10
F-RST# F-WP#
R-UB#
A/DQ3
R-CRE
WE#
C8
D8
E8
G8
H8
F8
A/DQ2
F-ACC
D9
E9
G9
F9
A/DQ9
V
D10
A19
E10
A18
F10
G10
CCQ
Shared Addresses
I n f o r m a t i o n )
A/DQ8
A/DQ1
F-CE#
RFU
A21-A16
A20-A16
A19-A16
A20-A16
A19-A16
A18-A16
C11
D11
A17
E11
G11
H11
RFU
F11
A/DQ0
D12
V
OE#
C12
A22
E12
G12
H12
F12
NC
NC
SSQ
S71NS-N_00_A9 April 15, 2009
A14
K14
NC
NC
Shared ADQ Pins
ADQ15 – ADQ0
(Distance between
outer NC balls
Reserved for
Shared Only
No Connect
is 2x pitch)
Future Use
Flash Only
Flash/RAM
RAM Only
Legend