PF38F6070M0Y0BFA Micron Technology Inc, PF38F6070M0Y0BFA Datasheet - Page 20
PF38F6070M0Y0BFA
Manufacturer Part Number
PF38F6070M0Y0BFA
Description
Manufacturer
Micron Technology Inc
Datasheet
1.PF38F6070M0Y0BFA.pdf
(102 pages)
Specifications of PF38F6070M0Y0BFA
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Table 8:
Datasheet
20
F[2:1]-VCC
P-Mode,
F-RST#
F-VPEN
F-WP#
R-UB#
R-LB#
F-VPP,
S-VCC
P-VCC
ADV#
P-CRE
VCCQ
WAIT
VSS
RFU
DU
Signal Descriptions - QUAD+ Package (Sheet 2 of 2)
Output
Power
Power
Power
Power
Power
Power
Input
Input
Input
Input
Input
—
—
WAIT: Output signal.
Indicates invalid data during synchronous array or non-array flash reads. Read Configuration Register
bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is
deasserted; WAIT is not gated by F-OE#.
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash die.
ADDRESS VALID: Low-true input.
During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on
the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous flash read operations, addresses are latched on the rising edge of ADV#, or are
continuously flow-through when ADV# is kept asserted.
RAM UPPER / LOWER BYTE ENABLES: Low-true input.
During RAM read and write cycles, R-UB# low enables the RAM high order bytes on D[15:8], and R-
LB# low enables the RAM low-order bytes on D[7:0].
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die and are RFU on
flash-only stacked combinations.
FLASH RESET: Low-true input.
F-RST# low initializes flash internal circuitry and disables flash operations. F-RST# high enables flash
operation. Exit from reset places the flash in asynchronous read array mode.
P-Mode (PSRAM Mode): Low-true input.
P-Mode is used to program the Configuration Register, and enter/exit Low Power Mode of PSRAM die.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-CRE (PSRAM Configuration Register Enable): High-true input.
P-CRE is high, write operations load the refresh control register or bus control register.
P-CRE is applicable only on combinations with synchronous PSRAM die.
P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die.
FLASH PROGRAM AND ERASE POWER: Valid F-V
operations.
Flash memory array contents cannot be altered when F-V
operations at invalid F-V
datasheet for additional details.
F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products.
FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies
power to the core logic of flash die #2 and flash die #3. Write operations are inhibited when F-V
V
F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked
combinations with only one flash die.
SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations
without SRAM die.
PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations
without PSRAM die.
DEVICE I/O POWER: Supply power for the device input and output buffers.
DEVICE GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements. Contact
Numonyx regarding the use of balls designated RFU.
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
• In synchronous array or non-array flash read modes, WAIT indicates invalid data when asserted
• In asynchronous flash page read, and all flash write modes, WAIT is asserted.
• F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked with
• F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with
LKO
and valid data when deasserted.
software commands.
software commands.
. Device operations at invalid F-V
PP
(F-V
PEN
) voltages should not be attempted. Refer to flash discrete product
CC
voltages should not be attempted.
PP
voltage on this ball enables flash program/erase
Numonyx™ Wireless Flash Memory (W18)
Numonyx™ Wireless Flash Memory (W18)
PP
(F-V
PEN
) < V
PPLK
(V
Order Number: 290701-18
PENLK
). Erase / program
November 2007
CC
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