MC33910BACR2 Freescale, MC33910BACR2 Datasheet - Page 84

• Manufacturer Part Number: MC33910BACR2
• Manufacturer: Freescale

Specifications of MC33910BACR2

• Lead Free Status / RoHS Status: Compliant

MXx - Analog Multiplexer Input Select
multiplexed to the ADOUT0 pin according to
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Table 54.
Configuration Register - CFR
HVDD - Hall Sensor Supply Enable
sensor supply.
CYSX8 - Cyclic Sense Timing x 8
shown in
Interrupt Mask Register - IMR
respective flags within the ISR will continue to work but will
not generate interrupts to the MCU. The 5.0 V Regulator
over-temperature prewarning interrupt and under-voltage
(VSUV) interrupts can not be masked and will always cause
an interrupt.
Analog Integrated Circuit Device Data
Freescale Semiconductor
MX2
These write-only bits selects which analog input is
When disabled or when in Stop or Sleep mode, the output
This register controls the cyclic sense timing multiplier.
This write-only bit enables/disables the state of the hall
1 = HVDD on
0 = HVDD off
This write-only bit influences the Cyclic Sense period as
1 = Multiplier enabled
0 = None
This register allow to mask some of interrupt sources. The
Table 55. Configuration Register - $D
0
0
0
0
1
1
1
1
Condition
Reset
Value
Reset
Write
Table
Analog Multiplexer Channel Select
MX1
0
0
1
1
0
0
1
1
POR, Reset
ext_reset
mode or
51.
C3
0
0
MX0
0
1
0
1
0
1
0
1
CYSX8
POR
C2
0
Die Temperature Sensor
VSENSE input
POR
C1
Reserved
Reserved
Reserved
Reserved
0
0
Meaning
Disabled
L1 input
Table
POR
C0
0
0
54.
ISR.
HSM - High Side Interrupt Mask
the high side block.
LINM - LIN Interrupts Mask
the LIN block.
VMM - Voltage Monitor Interrupt Mask
the voltage monitor block. The only maskable interrupt in the
voltage monitor block is the V
Interrupt Source Register - ISR
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
mask register (IMR).
ISRx - Interrupt Source Register
Table
interrupt sources are handled sequentially multiplex.
Writing to the interrupt mask register (IMR) will return the
This write-only bit enables/disables interrupts generated in
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = Interrupts Enabled
0 = Interrupts Disabled
This register allows the MCU to determine the source of
This register is also returned when writing to the interrupt
These read-only bits indicate the interrupt source following
In case more than one interrupt is pending, than the
Table 56. Interrupt Mask Register - $E
Reset Condition
58. If no interrupt is pending than all bits are 0.
Reset Value
Table 57. Interrupt Source Register - $E/$F
Write
Read
ISR3
S3
HSM
C3
LOGIC COMMANDS AND REGISTERS
1
FUNCTIONAL DEVICE OPERATIONS
ISR2
S2
SUP
C2
-.
1
over-voltage interrupt.
POR
ISR1
S1
LINM
C1
1
ISR0
S0
VMM
C0
1
33910
84