MC33910BACR2 Freescale, MC33910BACR2 Datasheet - Page 44

• Manufacturer Part Number: MC33910BACR2
• Manufacturer: Freescale

Specifications of MC33910BACR2

• Lead Free Status / RoHS Status: Compliant

Configuration Register - CFR
disable and the cyclic sense timing multiplier.
HVDD - Hall Sensor Supply Enable
sensor supply.
CYSX8 - Cyclic Sense Timing x 8.
Wake-up period as shown in
Interrupt Mask Register - IMR
sources. No interrupt will be generated to the MCU and no
flag will be set in the ISR register. The 5.0V Regulator over-
temperature prewarning interrupt and Under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
44
33910
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
This register controls the Hall Sensor Supply enable/
This write-only bit enables/disables the state of the hall
1 = HVDD on
0 = HVDD off
This write-only bit influences the cyclic sense and Forced
1 = Multiplier enabled
0 = None
This register allows masking of some of the interrupt
Writing to the IMR will return the ISR.
Table 27. Configuration Register - $D
Condition
Reset
Value
Reset
Write
Table 28. Interrupt Mask Register - $E
Condition
Reset
Reset
Value
Write
POR, Reset
ext_reset
mode or
HVDD
C3
0
HSM
C3
1
CYSX8
POR
C2
0
C2
Table
0
1
POR
23.
LINM
C1
POR
1
C1
0
0
VMM
C0
1
POR
C0
0
0
HSM - High Side Interrupt Mask
the high side block.
LINM - LIN Interrupts Mask
the LIN block.
VMM - Voltage Monitor Interrupt Mask
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V
Interrupt Source Register - ISR
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
Mask Register (IMR).
ISRx - Interrupt Source Register
Table
sources are handled sequentially multiplex.
This write-only bit enables/disables interrupts generated in
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = Interrupts Enabled
0 = Interrupts Disabled
This register allows the MCU to determine the source of
This register is also returned when writing to the Interrupt
These read-only bits indicate the interrupt source following
In case more than one interrupt is pending, the interrupt
30. If no interrupt is pending then all bits are 0.
Table 29. Interrupt Source Register - $E/$F
Read
ISR3
S3
Analog Integrated Circuit Device Data
ISR2
S2
SUP
over-voltage interrupt.
Freescale Semiconductor
ISR1
S1
ISR0
S0