STAC9752AXTAED1X IDT, Integrated Device Technology Inc, STAC9752AXTAED1X Datasheet - Page 76

• Manufacturer Part Number: STAC9752AXTAED1X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of STAC9752AXTAED1X

• Lead Free Status / RoHS Status: Compliant

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
Bit(s) Reset Value
14-11
9-5
15
10
D15
DL2
G4
D7
Default: 00xxh, see table 23: page77.
0
0
D14
DL1
G3
D6
DL4:DL0
G3:G0
Name
INV
G4
D13
DL0
G2
D5
Gain Sign Bit: The CODEC updates this bit with the sign of the gain value
present in G[3:0]. The BIOS updates this to take into consideration external
amplifiers or other external logic when relevant.
G[4] indicates whether the value is a gain or attenuation.
Gain in the G4 bit is in terms of dB.
This bit is Read/Write and only reset on POR and not by RESET#.
Gain Bits: The CODEC updates these bits with the gain value (dB relative to
level-out) in 1.5dBV increments. The BIOS updates these to take into
consideration external amplifiers or other external logic when relevant.
G[0:3] indicates the magnitude of the gain. G[4] indicates whether the value is a
gain or attenuation.
For Gain/Attenuation settings, see Table 24: page77.
These bits are read/write and are not reset on RESET#.
Inversion bit: Indicates that the CODEC presents a 180 degree phase shift to the
signal.
0h - No inversion reported
1h - Inverted
This bit is read/write and is not reset on RESET#.
BIOS should invert for each inverting gain stage.
Buffer delays: CODEC will provide number a delay measurement for the input
and output channels. Software will use this value to accurately calculate audio
stream position with respect to what is been reproduced or recorded. These
values are in 20.83 sec (1/48000 second) units.
For output channels, this timing is from the end of AC Link frame in which the
sample is provided, until the time the analog signal appears at the output pin. For
input streams, this is from when the analog signal is presented at the pin until the
representative sample is provided on the AC Link.
Analog in and out paths are not considered as part of this delay.
The measurement is a 'typical' measurement, at a 48KHz sample rate, with
minimal in-CODEC processing (i.e., 3D effects are turned off.)
These bits are read/write and are not reset on RESET#.
The default value is the delay internal to the CODEC. The BIOS may add to this
value the known delays external to the CODEC, such as for an external
amplifier.
01h…1Eh - Buffer delay in 20.83 sec units
1Fh - reserved
00h - Information not provided
D12
76
G1
D4
IV
D11
G0
D3
Description
Reserved
STAC9752A/9753A
D10
INV
D2
DL4
D9
D1
PC AUDIO
DL3
FIP
V 1.5 1206
D8
D0