STAC9752AXTAED1X IDT, Integrated Device Technology Inc, STAC9752AXTAED1X Datasheet - Page 39

• Manufacturer Part Number: STAC9752AXTAED1X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of STAC9752AXTAED1X

• Lead Free Status / RoHS Status: Compliant

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
5.4.1.
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97
CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit
position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the
AC‘97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transi-
tions and subsequent sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by the AC‘97 CODEC. SDATA_IN data is
sampled on the falling edges of BIT_CLK.
Slot 0: TAG
Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97
CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that
the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deasser-
tion of power on reset for example, while the AC‘97 CODEC’s voltage references settle. When the
AC-Link “CODEC Ready” indicator bit is a 1 it indicates that the AC-Link and AC‘97 CODEC control
and status registers are in a fully operational state. CODEC must assert “CODEC Ready” within
400 s after it starts receiving valid SYNC pulses from the controller, to provide indication of connec-
tion to the link and Control/Status registers are available for access. The AC’97 Controller and
related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set
SDATA_IN
BIT_CLK
End of previous audio frame
SYNC
S D A T A _ I N
B I T _ C L K
12.288 MHz
E n d o f p r e v i o u s a u d i o f r a m e
Frame
valid
S Y N C
Figure 18. Start of an Audio Input Frame
slot1
Tag Phase
slot2
("1" = time slot contains valid PCM data)
Time Slot "Valid" Bits
slot(12)
"0"
39
"0"
d e t e c t e d
S Y N C
"0"
C o d e c
R e a d y
19
Slot 1
s l o t 1
S D A T A _ O U T
"0"
b i t o f f r a m e
19
f i r s t
STAC9752A/9753A
s l o t 2
Slot 2
20.8 uS (48 kHZ)
Data Phase
"0"
19
Slot 3
"0"
PC AUDIO
19
Slot 12
V 1.5 1206
"0"