STAC9752AXTAED1X IDT, Integrated Device Technology Inc, STAC9752AXTAED1X Datasheet - Page 65

• Manufacturer Part Number: STAC9752AXTAED1X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of STAC9752AXTAED1X

• Lead Free Status / RoHS Status: Compliant

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
Bit(s) Reset Value
14-11
9:6
5:4
15
10
3
2
1
0
7.1.20.1.
The Extended Audio Status Control register also contains one active bit to enable or disable the
Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA bit D0 is 1, the variable sam-
ple rate control registers (2Ch and 32h) are active, and “on-demand” slot data required transfers are
allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48KHz data rate.
The STAC9752A/9753A supports “on-demand” slot request flags. These flags are passed from the
CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active
0
0
0
0
0
0
Variable Rate Sampling Enable
SPSA1:SPSA0
VRA Enable
Reserved
Reserved
Reserved
Reserved
SPDIF
VCFG
Name
SPCV
Determines the SPDIF transmitter behavior when data is not being
transmitted. When asserted, this bit forces the deassertion of the SPDIF
“Validity” flag, which is bit 28 transmitted by the SPDIF sub-frame. The “V” bit
is defined in the SPDIF Control Register (Reg 3Ah).
If “V” = 1 and “VCFG” = 0, then for each S/PDIF sub-frame (Left & Right),
bit<28> “Validity” flag reflects whether or not an internal CODEC transmission
error has occurred. Specifically an internal CODEC error should result in the
“Validity” flag being set to 1.
If “V” = 0 and “VCFG” = 1, In the case where the S/PDIF transmitter does not
receive a valid sample from the AC'97 controller, (Left or Right), the S/PDIF
transmitter should set the “Validity” flag to 0 and pad the “Audio Sample
Word” with 0s for sub-frame in question. If a valid sample (Left or Right) was
received and successfully transmitted, the “Validity” flag should be 0 for that
sub-frame.
Default state, coming out of reset, for “V” and “VCFG” should be 0 and 0.
These bits are set-able via driver .inf options.
Reserved
0 = invalid SPDIF configuration
1 = valid SPDIF configuration
Bit not used, should read back 0
SPDIF slot assignment
If CID[1:0] = 00 then SPSA[1:0] resets to 01
If CID[1:0] = 01 then SPSA[1:0] resets to 10
If CID[1:0] = 10 then SPSA[1:0] resets to 10
If CID[1:0] = 11 then SPSA[1:0] resets to 11
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
Reserved
0 = disables SPDIF (SPDIF_OUT is high-Z ) (Note 1)
1 = enable SPDIF
SPDIF is a control register for Reg 3Ah, this bit must be set low (i.e. SPDIF
disabled) in order to write to Reg 3Ah Bits D15, D13:D0.
Bit not used, should read back 0
0 = VRA disabled, DAC and ADC set to 48KHz (Registers 2Ch and 32h
loaded with the value BB80h)
1 = VRA enabled, Reg. 2Ch & 32h control sample rate
65
Description
STAC9752A/9753A
PC AUDIO
V 1.5 1206