SGTL5000XNLA3R2 Freescale, SGTL5000XNLA3R2 Datasheet - Page 26

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SGTL5000XNLA3R2

Manufacturer Part Number
SGTL5000XNLA3R2
Description
Manufacturer
Freescale
Datasheet

Specifications of SGTL5000XNLA3R2

Single Supply Voltage (typ)
1.8/2.5/3.3V
Lead Free Status / RoHS Status
Compliant

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Freescale Bass Enhance
typically controlled by the end-user. End-user driven
programming steps are shown in
Configuration.
change in the input signal level and BASS_LEVEL value of
0x001F adds some harmonic boost to the main signal. The
default settings should work for most applications. This
optional programming step shows how to configure a
different value.
7-Band Parametric EQ / 5-Band Graphic EQ / Tone
Control
pseudocode in this section shows how to select each block.
controlled by end-user. End-user driven programming steps
are shown in
Automatic Volume Control (AVC)
end-user. End-user driven programming steps are shown in
End-user Driven Chip
applications. However, the following example shows how to
change the configuration if needed.
26
SGTL500
FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
// Configure the surround width
// (0x0 = Least width, 0x7 = Most width). This example shows
// a width setting of 5
Modify DAP_SGTL_SURROUND->WIDTH_CONTROL 0x0005
// bits 6:4
The Freescale Bass Enhance on/off function will be
The default LR_LEVEL value of 0x0005 results in no
// Gain up the input signal level
Modify DAP_BASS_ENHANCE_CTRL->LR_LEVEL 0x0002
// bits 7:4
// Add harmonic boost
Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL 0x003F);
// bits 6:0
Only one audio EQ block can be used at a given time. The
Some parameters of the audio EQ will typically be
// 7-Band PEQ Mode
// Select 7-Band PEQ mode and enable 7 PEQ filters
Write DAP_AUDIO_EQ 0x0001
Write DAP_PEQ 0x0007
// Tone Control mode
Write DAP_AUDIO_EQ 0x0002
// 5-Band GEQ Mode
Write DAP_AUDIO_EQ 0x0003
The AVC on/off function will be typically controlled by the
The default configuration of the AVC should work for most
// Configure threshold to -18dB
Write DAP_AVC_THRESHOLD 0x0A40
// Configure attack rate to 16dB/s
Write DAP_AVC_ATTACK 0x0014
End-user Driven Chip
Configuration.
End-user Driven Chip
Configuration.
I
of data in I
modified by setting various bit-fields in CHIP_I2S_CTRL
register.
VOLUME CONTROL
is complete.
2
S CONFIGURATION
// Configure decay rate to 2dB/s
Write DAP_AVC_DECAY 0x0028
By default the I
The outputs should be unmuted after all the configuration
//---------------- Input Volume Control---------------------
// Configure ADC left and right analog volume to desired default.
// Example shows volume of 0dB
Write CHIP_ANA_ADC_CTRL 0x0000
// Configure MIC gain if needed. Example shows gain of 20dB
Modify CHIP_MIC_CTRL->GAIN 0x0001
// bits 1:0
//---------------- Volume and Mute Control---------------------
// Configure HP_OUT left and right volume to minimum, unmute
// HP_OUT and ramp the volume up to desired volume.
Write CHIP_ANA_HP_CTRL 0x7F7F
Modify CHIP_ANA_CTRL->MUTE_HP 0x0000
// bit 5
// Code assumes that left and right volumes are set to same value
// So it only uses the left volume for the calculations
usCurrentVolLeft = 0x7F;
usNewVolLeft = usNewVol & 0xFF;
usNumSteps = usNewVolLeft - usCurrentVolLeft;
if (usNumSteps == 0) return;
// Ramp up
for (int i = 0; i < usNumSteps; i++)
{
}
// LINEOUT and DAC volume control
Modify CHIP_ANA_CTRL->MUTE_LO 0x0000
// bit 8
// Configure DAC left and right digital volume. Example shows
// volume of 0dB
Write CHIP_DAC_VOL 0x3C3C
Modify CHIP_ADCDAC_CTRL->DAC_MUTE_LEFT 0x0000
// bit 2
Modify CHIP_ADCDAC_CTRL->DAC_MUTE_RIGHT 0x0000
// bit 3
// Unmute ADC
Modify CHIP_ANA_CTRL->MUTE_ADC 0x0000
// bit 0
++usCurrentVolLeft;
usCurrentVol = (usCurrentVolLeft << 8) | (usCurrentVolLeft);
Write CHIP_ANA_HP_CTRL usCurrentVol;
2
S format with SCLK set for 64*Fs. This can be
2
S port on the chip is configured for 24-bits
Analog Integrated Circuit Device Data
Freescale Semiconductor

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