SGTL5000XNLA3R2 Freescale, SGTL5000XNLA3R2 Datasheet - Page 22

• Manufacturer Part Number: SGTL5000XNLA3R2
• Manufacturer: Freescale

Specifications of SGTL5000XNLA3R2

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

AVC can apply a maximum gain of up to 12 dB. The
maximum gain can be selected, either 0, 6, or 12 dB. When
the maximum gain is set to 0 dB the AVC acts as a limiter. In
this case the AVC will only take effect when the signal level
is above the threshold.
to the threshold is called the attack rate. Too high of an attack
will cause an unnatural sound as the input signal is distorted.
Too low of an attack may cause saturation of the output as
the incoming signal will not be compressed quickly enough.
The attack rate is programmable with allowed range of
0.05 dB/s to 200 dB/s.
volume up until either the threshold or the maximum gain is
reached. The rate at which this volume is changed is called
the decay rate. The decay rate is programmable with allowed
range of 0.8 dB/s to 3200 dB/s. It is desirable to use very slow
decay rate to avoid any distortion in the signal and prevent
the AVC from entering a continuous attack-decay loop.
Volume Control (AVC) On/Off
that shows how to configure AVC and how to enable/disable
AVC respectively.
CONTROL
The CTRL_MODE pin chooses which mode will be used.
When CTRL_MODE is tied to ground, the control mode is
I
is SPI.
communication with the SGTL5000 including startup
configuration, routing, volume, etc.
22
SGTL500
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
2
C. When CTRL_MODE is tied to VDDIO, the control mode
When the measured audio level is below threshold, the
The rate at which the incoming signal is attenuated down
When the signal is below the threshold, AVC will adjust the
Refer to
The SGTL5000 supports both I
Regardless of the mode, the control interface is used for all
Automatic Volume Control (AVC)
Dual Input Mixer
Start Condition
Input from
I2C Address
for a programming example
DAP_AVC_THRESHOLD
2
C and SPI control modes.
Threshold
Compare
R/W ACK
Level
Figure 16. DAP AVC Block Diagram
and
Figure 17. Functional I
A15
Automatic
A8
ACK
DAP_AVC_THRESHOLD -> MAX_GAIN
A7
I
specification v2.0. The I
all registers.
address is 0n01010(R/W) where n is determined by
I2C_ADR0_CS and R/W is the read/write bit from the I
protocol.
is always 0001010(R/W).
which means that an external master will always drive
CTRL_CLK.
location is 16 bits wide.
• Start condition
• Device address with the R/W bit cleared to indicate write
• Send two bytes for the 16 bit register address (most
• Send two bytes for the 16 bits of data to be written to the
• Stop condition
• Start condition
• Device address with the R/W bit cleared to indicate write
• Send two bytes for the 16 bit register address (most
• Stop Condition followed by start condition (or a single
• Device address with the R/W bit set to indicate read
• Read two bytes from the addressed register (most
• Stop condition
2
Decay (0.05dB/s to ~200dB/s)
Attack (0.8dB/s to ~3200dB/s)
C
The I
For the 32 QFN version of the SGTL5000, the I
For the 20 QFN version of the SGTL5000 the I
The SGTL5000 is always the slave on all transactions
In general an I
All locations are accessed with a 16 bit address. Each
An example I
significant byte first)
register (most significant byte first)
An I
significant byte first)
restart condition)
significant byte first)
Figure 17
2
C Diagram
DAP_AVC_DECAY
DAP_AVC_ATTACK
2
C read transaction is defined as follows:
2
If < Threshold
C port is implemented according to the I
A0
If > Threshold
Volume
Control
ACK
shows the functional I
D15
2
C write transaction follows:
2
C transaction looks as follows.
Analog Integrated Circuit Device Data
2
C interface is used to read and write
D8
ACK
SGTL Surround
D7
2
Freescale Semiconductor
Output To
C timing diagram.
Stop Condition
D0
ACK
2
2
C address
C
2
C device
2
C