AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 21

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the sampling
rate and serial clock rate chosen. The following relationship
details the restrictions in configuring a codec cascade.
When using the indirectly coupled frame sync configuration in
cascaded operation, it is necessary to be aware of the restrictions
in sending data to all devices in the cascade. Effectively the time
allowed is given by the sampling interval (M/DMCLK, where M
can be one of 256, 512, 1024 or 2048) which is 125 µs for a
sample rate of 8 kHz. In this interval, the DSP must transfer
N × 16 bits of information, where N is the number of devices in
the cascade. Each bit will take 1/SCLK and, allowing for any
latency between the receipt of the Rx interrupt and the trans-
mission of the Tx data, the relationship for successful operation
is given by:
The interrupt latency will include the time between the ADC
sampling event and the RX interrupt being generated in the
DSP—this should be 16 SCLK cycles.
As the AD73422 is configured in Cascade Mode, each device
must know the number of devices in the cascade because the
Data and Mixed modes use a method of counting input frame
sync pulses to decide when they should update the DAC
register from the serial input register. Control Register A con-
tains a 3-bit field (DC0–2) that is programmed by the DSP
during the programming phase. The default condition is that the
field contains 000b, which is equivalent to a single device in
cascade (see Table XIX). However, for cascade operation this
field must contain a binary value that is one less than the number
of devices in the cascade, which is 001b for a single AD73422
device configuration.
DC2
0
0
0
0
1
1
1
1
REV. 0
Number of Codecs × Word Size (16) × Sampling Rate ≤ Serial
SECTION
Figure 11. Directly Coupled or Frame Sync Loop-
Back Configuration
M/DMCLK > ((N × 16/SCLK) + T
DSP
Table XIX. Device Count Settings
DC1
0
0
1
1
0
0
1
1
TFS (0/1)
DT (0/1)
SCLK (0/1)
DR (0/1)
RFS (0/1)
AD73422
Clock Rate
SDOFS
DC0
0
1
0
1
0
1
0
1
SCLK2
SDIFS
SDO
SDI
INTERRUPT LATENCY
CHANNEL 1
CHANNEL 2
Cascade Length
1
2
3
4
5
6
7
8
SECTION
AFE
)
–21–
FUNCTIONAL DESCRIPTION—DSP
The AD73422 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The AD73422 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
Figure 12 is an overall block diagram of the AD73422. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73422 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
GENERATORS
DAG 1
ADDRESS
ALU
DATA
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
Figure 12. Functional Block Diagram
SEQUENCER
PROGRAM
SHIFTER
DATA MEMORY DATA
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
REF
ADC1
(OPTIONAL
SPORT 0
16K PM
ANALOG FRONT END
SERIAL PORTS
POWER-DOWN
8K)
DAC1
CONTROL
MEMORY
SERIAL PORT
SECTION
SPORT 2
(OPTIONAL
SPORT 1
16K DM
8K)
ADC2
TIMER
PROGRAMMABLE
DAC2
FLAGS
AND
I/O
AD73422
FULL MEMORY
CONTROLLER
HOST MODE
EXTERNAL
EXTERNAL
EXTERNAL
BYTE DMA
ADDRESS
INTERNAL
MODE
DATA
DATA
PORT
BUS
DMA
BUS
BUS
OR