AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 14

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

AD73422
SPORT2 Overview
SPORT2 is a flexible, full-duplex, synchronous serial port
whose protocol has been designed to allow extra AFE devices
(AD733xx series), up to a maximum of eight I/O channels, to be
connected in cascade to a DSP SPORT (0 or 1). It has a very
flexible architecture that can be configured by programming two
of the internal control registers in each AFE block. SPORT2 has
three distinct modes of operation: Control Mode, Data Mode
and Mixed Control/Data Mode.
NOTE: As each AFE has its own control section, the register
settings in each must be programmed. The registers that control
serial transfer and sample rate operation (CRA and CRB) must
be programmed with the same values, otherwise incorrect opera-
tion may occur.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), information
that is sent to the device is used to update the decoder section
(DAC), while the encoder section (ADC) data is read from the
device. In this mode, only DAC and ADC data is written to or
read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)
allows the user to choose whether the information being sent to
the device contains either control information or DAC data.
This is achieved by using the MSB of the 16-bit frame as a flag
bit. Mixed mode reduces the resolution to 15 bits with the MSB
being used to indicate whether the information in the 16-bit
frame is control information or DAC/ADC data.
SPORT2 features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must
be written to SPORT2 without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once SPORT2 starts to output
the latest ADC word, it is safe for the DSP to write new control
or data words to the codec. In certain configurations, data can
be written to the device to coincide with the output sample
being shifted out of the serial register—see section on AFE
REGISTER
CONTROL
SE
RESET
SDIFS
SDI
1A
8
(EXTERNAL)
DIVIDER
AMCLK
AMCLK
3
REGISTER
CONTROL
1B
DMCLK
(INTERNAL)
CONTROL
REGISTER
CONTROL
REGISTER
16
8
SERIAL REGISTER 1
1G
1H
SERIAL PORT 1
REGISTER
CONTROL
(SPORT 1)
8
1C
REGISTER
CONTROL
8
8
1F
REGISTER
CONTROL
1D
Figure 8. SPORT2 Block Diagram
DIVIDER
SCLK
2
CONTROL
REGISTER
8
1E
SCLK
(SDOFS1)
(SDO1)
–14–
interfacing. The serial clock rate (CRB:2–3) defines how many
16-bit words can be written to a device before the next output
sample event will happen.
The SPORT2 block diagram, shown in Figure 8, details the
blocks associated with codecs 1 and 2, including the eight con-
trol registers (A–H), external AMCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73422 features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to gen-
erate a lower frequency master clock internally in the codec
which may be more suitable for either serial transfer or sampling
rate requirements. The master clock divider has five divider
options (÷ 1 default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by
loading the master clock divider field in Register B with the appro-
priate code. Once the internal device master clock (DMCLK) has
been set using the master clock divider, the sample rate and
serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK)
rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or
DMCLK/8, where DMCLK is the internal or device master
clock resulting from the external or pin master clock being di-
vided by the master clock divider. When working at the lower
SCLK rate of DMCLK/8, which is intended for interfacing with
slower DSPs, the SPORT will support a maximum of two codecs
in cascade (a single AD73422 or two AD73311s) with the sample
rate of DMCLK/256.
SPORT2 Register Maps
There are two register banks for each AFE channel in the
AD73422: the control register bank and the data register bank.
The control register bank consists of eight read/write registers,
each eight bits wide. Table IX shows the control register map
for the AD73422. The first two control registers, CRA and
CRB, are reserved for controlling serial activity. They hold
settings for parameters such as serial clock rate, internal master
clock rate, sample rate and device count. As both codecs are
internally cascaded, registers CRA and CRB on each codec
must be programmed with the same setting to ensure correct
operation (this is shown in the programming examples). The
REGISTER
CONTROL
SE
RESET
(SDIFS2)
(SDI2)
2A
8
(EXTERNAL)
DIVIDER
AMCLK
AMCLK
3
REGISTER
CONTROL
2B
REGISTER
REGISTER
DMCLK
(INTERNAL)
CONTROL
CONTROL
16
8
SERIAL REGISTER
2G
2H
SERIAL PORT 2
REGISTER
(SPORT 2)
CONTROL
8
2C
REGISTER
CONTROL
8
8
2F
REGISTER
CONTROL
2D
DIVIDER
SCLK
2
REGISTER
CONTROL
8
SDOFS
2E
SDO
REV. 0