AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 15

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

other five registers; CRC through CRH are used to hold control
settings for the ADC, DAC, Reference, Power Control and
Gain Tap sections of the device. It is not necessary that the
contents of CRC through CRH on each codec are similar. Con-
trol registers are written to on the negative edge of SCLK. The
data register bank consists of two 16-bit registers that are the
DAC and ADC registers.
Master Clock Divider
The AD73422’s AFE features a programmable master clock
divider that allows the user to reduce an externally available
master clock, at pin AMCLK, by one of the ratios 1, 2, 3, 4 or
5, to produce an internal master clock signal (DMCLK) that is
used to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table V
shows the division ratio corresponding to the various bit set-
tings. The default divider ratio is divide-by-one.
MCD2
0
0
0
0
1
1
1
1
Serial Clock Rate Divider
The AD73422’s AFE features a programmable serial clock
divider that allows users to match the serial clock (SCLK) rate
of the data to that of the DSP engine or host processor. The
maximum SCLK rate available is DMCLK, and the other avail-
able rates are: DMCLK/2, DMCLK/4 and DMCLK/8. The
slowest rate (DMCLK/8) is the default SCLK rate. The serial
clock divider is programmable by setting bits CRB:2–3. Table
VI shows the serial clock rate corresponding to the various bit
settings.
REV. 0
Table V. DMCLK (Internal) Rate Divider Settings
SCD1
0
0
1
1
Table VI. SCLK Rate Divider Settings
MCD1
0
0
1
1
0
0
1
1
Address (Binary)
000
001
010
011
100
100
100
100
SCD0
0
1
0
1
MCD0
0
1
0
1
0
1
0
1
SCLK Rate
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
Name
CRA
CRB
CRC
CRD
CRE
CRF
CRG
CRH
DMCLK Rate
AMCLK
AMCLK/2
AMCLK/3
AMCLK/4
AMCLK/5
AMCLK
AMCLK
AMCLK
Description
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Control Register F
Control Register G
Control Register H
Table IX. Control Register Map
–15–
Sample Rate Divider
The AD73422 features a programmable sample rate divider that
allows users flexibility in matching the codec’s ADC and DAC
sample rates (decimation/interpolation rates) to the needs of the
DSP software. The maximum sample rate available is DMCLK/
256, which offers the lowest conversion group delay, while the
other available rates are: DMCLK/512, DMCLK/1024 and
DMCLK/2048. The slowest rate (DMCLK/2048) is the default
sample rate. The sample rate divider is programmable by setting
bits CRB:0-1. Table VII shows the sample rate corresponding to
the various bit settings.
DAC Advance Register
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The de-
fault DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(F
rate F
and the Sample Rate divider; see Tables VII and IX. In certain
circumstances this DAC update adjustment can reduce the
group delay when the ADC and DAC are used to process data
in series. See AD73322 data sheet (Appendix C) for details of
how the DAC advance feature can be used.
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
DA4
0
0
0
—
1
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
S
is dependent on the setting of both the AMCLK divider
DA3
0
0
0
—
1
1
Table VII. Sample Rate Divider Settings
DIR1
0
0
1
1
Width
8
8
8
8
8
8
8
8
Table VIII. DAC Timing Control
DA2
0
0
0
—
1
1
Reset Setting (Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DIR0
0
1
0
1
S
× 32); see Table VIII. The sample
DA1
0
0
1
—
1
1
SCLK Rate
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
DA0
0
1
0
—
0
1
AD73422
Time Advance
0 s
1/(F
2/(F
—
30/(F
31/(F
S
S
S
S
× 32) s
× 32) s
× 32) s
× 32) s