AD73422BB-80 Analog Devices Inc, AD73422BB-80 Datasheet - Page 5

• Manufacturer Part Number: AD73422BB-80
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-80

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

POWER CONSUMPTION
Conditions
AFE SECTION
NOTES
The above values are in mA and are typical values unless otherwise noted.
Specifications subject to change without notice.
TIMING CHARACTERISTICS–AFE SECTION
Parameter
Clock Signals
Serial Port
NOTES
1
Specifications subject to change without notice.
REV. 0
For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
t
t
t
t
t
t
t
t
t
t
t
t
t
ADCs Only On
DACs Only On
ADCs and DACs On
ADCs and DACs
ADCs and DACs
All Sections On
REFCAP Only On
REFCAP and
All AFE Sections Off
All AFE Sections Off
1
2
3
4
5
6
7
8
9
10
11
12
13
and Input Amps On
and AGT On
REFOUT Only On
Limit
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
1
Typ
11.5
20
24.5
30
29
37
0.8
3.5
1.5
10 µA
1
1
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Max
12
22
27
34
32.5
43.5
1.25
4.75
3.0
40 µA
1
1
1
1
0
0
0
0
SE
1
1
Description
See Figure 1
16.384 MHz AMCLK Period
AMCLK Width High
AMCLK Width Low
See Figures 3 and 4
SCLK Period (SCLK = AMCLK)
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from AMCLK
1
–5–
AMCLK On
YES
YES
YES
YES
YES
YES
NO
NO
YES
NO
Test Conditions
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
AMCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
AD73422