AD73422BB-80 Analog Devices Inc, AD73422BB-80 Datasheet - Page 30

• Manufacturer Part Number: AD73422BB-80
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-80

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

AD73422
Bus Request and Bus Grant (Full Memory Mode)
The AD73422 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
AD73422 is not performing an external memory access, it re-
sponds to the active BR input in the following processor cycle
by:
• three-stating the data and address buses and the PMS, DMS,
• asserting the bus grant (BG) signal and
• halting program execution.
If Go Mode is enabled, the AD73422 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the AD73422 is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the proces-
sor cycle after the access completes. The instruction does not
need to be completed when the bus is granted. If a single in-
struction requires two external memory accesses, the bus will be
granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the AD73422 is ready to execute
an instruction, but is stopped because the external bus is already
granted to another device. The other device can release the bus
by deasserting bus request. Once the bus is released, the
AD73422 deasserts BG and BGH and executes the external
memory access.
Flag I/O Pins
The AD73422 has eight general-purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction, 1 =
output and 0 = input. The PFDATA register is used to read and
write the values on the pins. Data being read from a pin config-
ured as an input is synchronized to the AD73422’s clock. Bits
that are programmed as outputs will read the value being out-
put. The PF pins default to input during reset.
In addition to the programmable flags, the AD73422 has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1
and FL2. FL0–FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTION
The AD73422 assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and readabil-
ity. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryp-
BMS, CMS, IOMS, RD, WR output drivers,
tic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
–30–
• Every instruction assembles into a single, 24-bit word that
• The syntax is a superset ADSP-2100 Family assembly language
• Sixteen condition codes are available. For conditional jump,
• Multifunction instructions allow parallel execution of an
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The AD73422 has on-chip emulation support and an ICE-Port,
a special set of pins that interface to the EZ-ICE. These features
allow in-circuit emulation without replacing the target system
processor by using only a 14-pin connection from the target
system to the EZ-ICE. Target systems must have a 14-pin con-
nector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
prior to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes), it
does not matter that the mode information is latched by an
emulator reset. However, if you are using the RESET pin as a
method of setting the value of the mode pins, you have to take
the effects of an emulator reset into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 20. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET or
ERESET pin.
The ICE-Port interface consists of the following AD73422 pins:
EBR
EMS
ELIN
These AD73422 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the AD73422
and the connector must be kept as short as possible, no longer
than three inches.
can execute in a single instruction cycle.
and is completely source and object code compatible with other
family members. Programs may need to be relocated to utilize
on-chip memory and conform to the AD73422’s interrupt
vector and reset vector map.
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
EBG
EINT
ELOUT
Figure 20. Mode A Pin/EZ-ICE Circuit
ERESET
ECLK
EE
1k
PROGRAMMABLE
I/O
ERESET
RESET
MODE A/PFO
AD73422
REV. 0