AD9842AJSTZRL Analog Devices Inc, AD9842AJSTZRL Datasheet - Page 22

• Manufacturer Part Number: AD9842AJSTZRL
• Manufacturer: Analog Devices Inc

Specifications of AD9842AJSTZRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

AD9841A/AD9842A
Internal Power-On Reset Circuitry
After power-on, the AD9842A will automatically reset all inter-
nal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset
operation is completed. Pin 43 (formerly RSTB on the AD9842A
non-A) is no longer used for the reset operation. Toggling Pin
43 in the AD9842A will have no effect.
Grounding and Decoupling Recommendations
As shown in Figures 33 and 34, a single ground plane is recom-
mended for the AD9841A/AD9842A. This ground plane should be
as continuous as possible, particularly around Pins 25 through
39. This will ensure that all analog decoupling capacitors provide
OUTPUTS
DATA
12
INTERFACE
SUPPLY
DRIVER
SERIAL
(MSB) D11
3V
D10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
0.1 F
10
11
12
1
2
3
4
5
6
8
9
3
7
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
ANALOG SUPPLY
0.1 F
(Not to Scale)
AD9842A
3V
TOP VIEW
43 42 41 40
ANALOG SUPPLY
3V
the lowest possible impedance path between the power and bypass
pins and their respective ground pins. All decoupling capaci-
tors should be located as close as possible to the package pins. A
single clean power supply is recommended for the AD9841A/AD9842A,
but a separate digital driver supply may be used for DRVDD
(Pin 13). DRVDD should always be decoupled to DRVSS (Pin
14), which should be connected to the analog ground plane.
Advantages of using a separate digital driver supply include using a
lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing
digital power dissipation, and reducing potential noise coupling.
If the digital outputs (Pins 3–12) must drive a load larger than
20 pF, buffering is recommended to reduce digital code transi-
tion noise. Alternatively, placing series resistors close to the
digital output pins may also help reduce noise.
39 38
37
0.1 F
1.0 F
1.0 F
0.1 F
36
35
34
33
32
31
30
29
28
26
25
8
27
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
BYP2
BYP1
AVDD1
AVSS
AVSS
CLOCK
INPUTS
NC = NO CONNECT
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
3V
ANALOG SUPPLY
3V
ANALOG SUPPLY
CCD SIGNAL