AD9842AJSTZRL Analog Devices Inc, AD9842AJSTZRL Datasheet - Page 19

• Manufacturer Part Number: AD9842AJSTZRL
• Manufacturer: Analog Devices Inc

Specifications of AD9842AJSTZRL

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

The same Bayer pattern can also be interlaced, and the VD
Selected mode should be used with this type of CCD (see Fig-
ure 27). The Color Steering performs the proper multiplexing of
the R, G, and B gain values (loaded into the PxGA gain regis-
ters), and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA Timing section. The PxGA gain for each of the four
channels is variable from –2 dB to +10 dB, controlled in 64 steps
through the serial interface. The PxGA gain curve is shown in
Figure 28.
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with 4 dB from the PxGA stage, the total gain range
for the AD984xA is 6 dB to 40 dB. The minimum gain of 6 dB
CCD: PROGRESSIVE BAYER
CCD: INTERLACED BAYER
(100000)
Gb
Gb
Gb
Gb
10
R
R
R
R
-2
Gb
Gb
8
6
4
2
0
R
R
32
ODD FIELD
EVEN FIELD
Gr
Gr
Gr
Gr
B
B
B
B
Gr
Gr
B
B
40
Gb
Gb
Gb
Gb
R
R
R
R
Gb
Gb
R
R
Gr
Gr
Gr
Gr
B
B
B
B
48
Gr
Gr
B
B
PxGA GAIN REGISTER CODE
LINE0
LINE1
LINE2
LINE0
LINE1
LINE2
LINE0
LINE1
LINE2
56
MOSAIC SEPARATE COLOR
STEERING MODE
VD SELECTED COLOR
STEERING MODE
0
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
8
16
24
(011111)
31
is needed to match a 1 V input signal with the ADC full-scale
range of 2 V. When compared to 1 V full-scale systems (such as
ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-
dB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Code Range Gain Equation (dB)
0–511
512 –1023
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 91 to 1023. The
Gain Accuracy Specifications also include the PxGA gain of 4 dB,
for a total gain range of 6 dB to 40 dB.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 64 LSB (AD9841A)
or 255 LSB (AD9842A) may be programmed, with 8-bit resolu-
tion. The resulting error signal is filtered to reduce noise, and
the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD984xA’s optical black
clamping may be disabled using Bit D5 in the Operation Register
(see Serial Interface Timing and Internal Register Description
section). When the loop is disabled, the Clamp Level Register
may still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the ability to track
low-frequency variations in the black level will be reduced.
36
30
24
18
12
6
0
0
127
Gain = 20 log
Gain = (0.0354)(code) – 0.4
255
VGA GAIN REGISTER CODE
383
10
AD9841A/AD9842A
([658 + code]/[658 – code]) – 0.4
511
639
767
895
1023