SC16C754BIBM-S NXP Semiconductors, SC16C754BIBM-S Datasheet - Page 11

• Manufacturer Part Number: SC16C754BIBM-S
• Manufacturer: NXP Semiconductors

Specifications of SC16C754BIBM-S

• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC16C754B_4
Product data sheet
Fig 6.
N = receiver FIFO trigger level.
The two blocks in dashed lines cover the case where an additional byte is sent, as described in
RTS functional timing
RTS
IOR
RX
6.2.1 Auto-RTS
6.2.2 Auto-CTS
Start
Auto-RTS data flow control originates in the receiver block (see
SC16C754B”).
used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the
halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is
de-asserted. The sending device (for example, another UART) may send an additional
byte after the trigger level is reached (assuming the sending UART has another byte to
send) because it may not recognize the de-assertion of RTS until it has begun sending the
additional byte. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be de-asserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.
Fig 7.
CTS
TX
byte N
When CTS is LOW, the transmitter keeps sending serial data out.
When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter
finishes sending the current byte, but it does not send the next byte.
When CTS goes from HIGH to LOW, the transmitter begins sending data again.
CTS functional timing
Stop
Figure 6
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Start
Rev. 04 — 6 October 2008
Start
shows RTS functional timing. The receiver FIFO trigger levels
byte 0 to 7
byte N
1
1
2
Stop
Stop
N
Start
Figure 1 “Block diagram of
Section
SC16C754B
N+1
byte 0 to 7
6.2.1.
002aaa226
© NXP B.V. 2008. All rights reserved.
Start
002aaa227
Stop
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