ICM7170IBG Intersil, ICM7170IBG Datasheet - Page 7

• Manufacturer Part Number: ICM7170IBG
• Manufacturer: Intersil

Specifications of ICM7170IBG

• Bus Type: Multiplexed
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOIC W
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 24
• Mounting: Surface Mount
• Date Format: Binary
• Time Format: Binary
• Lead Free Status / RoHS Status: Not Compliant

NOTES:
Addresses 10010 to 11111 (12h to 1Fh) are unused.
‘+’ Unused bit for interrupt Mask Register, MSB bit for interrupt Status Register.
‘-’ Indicates unused bits.
‘
‘M’ Alarm compare for particular counter will be enabled if bit is set to logic “0”.
Detailed Description
Oscillator
The ICM7170 has an onboard CMOS Pierce oscillator with an
internally regulated voltage supply for maximum accuracy,
stability, and low power consumption. It operates at any of
four popular crystal frequencies: 32.768kHz, 1.046576MHz,
2.097152MHz, and 4.194304MHz (Note 1). The crystal
should be designed for the parallel resonant mode of
oscillation. In addition to the crystal, 2 or 3 load capacitors are
required, depending on the circuit topology used.
The oscillator output is divided down to 4000Hz by one of
four divider ratios, determined by the two frequency
selection bits in the Command Register (D0 and D1 at
address 11H). This 4000Hz is then divided down to 100Hz,
which is used as the clock for the counters.
Time and calendar information is provided by 8 consecutive,
programmable counters: 100ths of, seconds, minutes,
hours, day of week, date, month, and year. The data is in
binary format with 8 bits per digit. See Table 3 for address
information. Any unused bits are held to a logic “0” during a
read and ignored during a write operation.
NOTE:
Alarm Compare RAM
On the chip are 51 bits of Alarm Compare RAM grouped into
words of different lengths. These are used to store the time,
ranging from 10ths of seconds to years, for comparison to the
real-time counters. Each counter has a corresponding RAM
†
Periodic and Alarm Flags
1. 4.94304MHz is not available over military temperature range.
’ AM/PM indicator bit in 12 hour format Logic “0” indicates AM, logic “1” indicates PM.
A4
0
1
1
GLOBAL INTERRUPT
A3
NOT USED
1
0
0
D7
D7
A2
ADDRESS
1
0
0
A1
1
0
0
A0
1
0
1
7
DAY
DAY
INTERRUPT STATUS REGISTER ADDRESS (10000b, 10h) READ-ONLY
D6
D6
←
←
INTERRUPT MASK REGISTER ADDRESS (10000b, 10h) WRITE-ONLY
HEX
0F
10
11
TABLE 3. ADDRESS CODES AND FUNCTIONS (Continued)
TABLE 4. INTERRUPT AND STATUS REGISTERS FORMAT
RAM-day of week
Interrupt Status and Mask
Register
Command register
HOUR
HOUR
D5
D5
FUNCTION
Periodic Interrupt Mask Bits
Periodic Interrupt Flags
MIN
MIN
D4
D4
ICM7170
SEC
SEC
D3
D3
word. In the Alarm Mode an interrupt is generated when the
current time is equal to the alarm time. The RAM contents are
compared to the counters on a word by word basis. If a
comparison to a particular counter is unnecessary, then the
appropriate ‘M’ bit in Compare RAM should be set to logic “1”.
The ‘M’ bit, referring to Mask bit, causes a particular RAM
word to be masked off or ignored during a compare. Table 3
shows addresses and Mask bit information.
Periodic Interrupts
The interrupt output can be programmed for 6 periodic
signals: 100Hz, 10Hz, once per second, once per minute,
once per hour, or once per day. The 100Hz and 10Hz
interrupts have instantaneous errors of ±2.5% and ±0.15%
respectively. This is because non-integer divider circuitry is
used to generate these signals from the crystal frequency,
which is a power of 2. The time average of these errors over
a 1 second period, however, is zero. Consequently, the
100Hz or 10Hz interrupts are not suitable as an aid in tuning
the oscillator; the 1 second interrupt must be used instead.
See General Notes, Note 6.
The periodic interrupts can occur concurrently and in
addition to alarm interrupts. The periodic interrupts are
controlled by bits in the interrupt mask register, and are
enabled by setting the appropriate bit to a “1” as shown in
Table 4. Bits D1 through D6 in the mask register, in
conjunction with bits D1 through D6 of the status register,
control the generation of interrupts according to Figure 5.
D7
M
+
-
D6
1/10 SEC
1/10 SEC
-
-
D2
D2
D5
-
D4
-
DATA
1/100 SEC
1/100 SEC
D1
D1
→
→
D3
-
D2
Alarm/Compare Mask Bit
Alarm Compare Flag
D1
ALARM
ALARM
D0
D0
D0
VALUE
0 - 6