ICM7170IBG Intersil, ICM7170IBG Datasheet

ICM7170IBG

Manufacturer Part Number

ICM7170IBG

Description

Manufacturer

Intersil

Datasheet

1.ICM7170IBG.pdf (14 pages)

Specifications of ICM7170IBG

Bus Type

Multiplexed

Operating Supply Voltage (typ)

2.5/3.3/5V

Package Type

SOIC W

Operating Supply Voltage (max)

5.5V

Operating Temperature Classification

Industrial

Operating Temperature (max)

85C

Operating Temperature (min)

-40C

Pin Count

Mounting

Surface Mount

Date Format

Binary

Time Format

Binary

Lead Free Status / RoHS Status

Not Compliant

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Microprocessor-Compatible,

Real-Time Clock

The ICM7170 real time clock is a microprocessor bus

compatible peripheral, fabricated using Intersil’s silicon gate

CMOS LSl process. An 8-bit bidirectional bus is used for the

data I/O circuitry. The clock is set or read by accessing the 8

internal separately addressable and programmable counters

from

a pulse train divided down from a crystal oscillator circuit,

and the frequency of the crystal is selectable with the

on-chip command register. An extremely stable oscillator

frequency is achieved through the use of an on-chip

regulated power supply.

The device access time (t

for wait states or software overhead with most

microprocessors. Furthermore, an ALE (Address Latch

Enable) input is provided for interfacing to microprocessors

with a multiplexed address/data bus. With these two special

features, the ICM7170 can be easily interfaced to any

available microprocessor.

The ICM7170 generates two types of interrupts, periodic and

alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be

programmed by the internal interrupt control register to

provide 6 different output signals. The alarm interrupt is set

by loading an on-chip 51-bit RAM that activates an interrupt

output through a comparator. The alarm interrupt occurs

when the real time counter and alarm RAM time are equal. A

status register is available to indicate the interrupt source.

An on-chip Power Down Detector eliminates the need for

external components to support the battery back-up

function. When a power down or power failure occurs,

internal logic switches the on-chip counters to battery back-

up operation. Read/write functions become disabled and

operation is limited to time-keeping and interrupt generation,

resulting in low power consumption.

Internal latches prevent clock roll-over during a read cycle.

Counter data is latched on the chip by reading the

100th-seconds counter and is held indefinitely until the

counter is read again, assuring a stable and reliable time

value.

100

seconds to years. The counters are controlled by

ACC

) of 300ns eliminates the need

Data Sheet

1-888-INTERSIL or 321-724-7143

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• 8-Bit, µP Bus Compatible

• Regulated Oscillator Supply Ensures Frequency Stability

• Time From 1/100 Seconds to 99 Years

• Software Selectable 12/24 Hour Format

• Latched Time Data Ensures No Roll Over During Read

• Full Calendar with Automatic Leap Year Correction

• On-Chip Battery Backup Switchover Circuit

• Access Time Less than 300ns

• 4 Programmable Crystal Oscillator Frequencies Over

• 3 Programmable Crystal Oscillator Frequencies Over

• On-Chip Alarm Comparator and RAM

• Interrupts from Alarm and 6 Selectable Periodic Intervals

• Standby Micro-Power Operation: 1.2µA Typical at 3.0V

Applications

• Portable and Personal Computers

• Data Logging

• Industrial Control Systems

• Point Of Sale

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Part Number Information

NOTE: “A” Parts Screened to <5µA I

PART NUMBER

ICM7170IPG

ICM7170IBG

ICM7170AIPG

ICM7170AIBG

- Multiplexed or Direct Addressing

and Low Power

Industrial Temperature Range

Military Temperature Range

and 32kHz Crystal

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

November 2003

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a registered trademark of Intersil Americas Inc.

TEMP. RANGE

-40× to 85×

(

24 Ld PDIP

24 Ld SOIC

24 Ld PDIP

24 Ld SOIC

STBY

PACKAGE

at 32kHz.

ICM7170

FN3019.6

E24.6

M24.3

E24.6

M24.3

PKG.

NO.

Related parts for ICM7170IBG

ICM7170IBG Summary of contents

Page 1

... Part Number Information TEMP. RANGE o PART NUMBER ( C) ICM7170IPG -40× to 85× ICM7170IBG -40× to 85× ICM7170AIPG -40× to 85× ICM7170AIBG -40× to 85× NOTE: “A” Parts Screened to <5µA I CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. ...

Page 2

Pinouts ICM7170 (PDIP) TOP VIEW WR 1 ALE OSC OUT 9 OSC IN 10 INT SOURCE 11 INTERRUPT 12 Functional Block Diagram µP WR ...

Page 3

Absolute Maximum Ratings T A Supply Voltage ...

Page 4

AC Electrical Specifications Load Capacitance = 150pF, V PARAMETER READ CYCLE TIMING READ to DATA Valid ADDRESS Valid to DATA Valid, t ACC READ Cycle Time, t CYC Read High Time ...

Page 5

Timing Diagrams (Continued A4 FIGURE 2. WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = A4 D7, CS ALE RD FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS (WR ...

Page 6

Pin Descriptions SIGNAL PIN NUMBER WR ALE CS A4-A0 OSC OUT OSC IN INT SOURCE INTERRUPT V (GND BACKUP COMMAND REGISTER ADDRESS (10001b, 11h) WRITE-ONLY n/a n/a Normal/Test Mode ...

Page 7

TABLE 3. ADDRESS CODES AND FUNCTIONS (Continued) ADDRESS HEX NOTES: Addresses 10010 to 11111 (12h to 1Fh) ...

Page 8

PERIODIC INT’ MASK BITS INTERRUPT MASK D7 D6 REGISTER NOT USED INTERRUPT STATUS D7 D6 REGISTER GLOBAL INTERRUPT FLAG BIT The interrupt status register, when read, indicates the cause of the interrupt and resets itself on the rising edge of ...

Page 9

POSITIVE SUPPLY RAIL (+5V PIN 23 BATTERY R2 V BACK 2K PIN PIN 13 DIGITAL GROUND FIGURE 6. SIMPLIFIED ICM7170 BATTERY BACKUP CIRCUIT Time Synchronization Time synchronization is achieved through bit D3 of the Command ...

Page 10

OSC IN OSC OUT 10 9 ICM7170 FIGURE 8. ORIGINAL OSCILLATOR CONFIGURATION The new load configuration (Figure 6) allows these two conditions to be met independently. The two load capacitors, C1 and C2, provide a ...

Page 11

I/O block address decoder. DS1 selects the interrupt priority used to isolate the ICM7170 from the PC databus for test purposes only required on heavily-loaded TTL databuses - the ICM7170 can drive most ...

Page 12

General Notes 1.TIME ACCESS - To update the present time registers (Hex 07) the / register must be read first. The 7 real time counter 100 registers (Hours, Minutes, Seconds, Month, Date, Day, and Year) data are ...

Page 13

Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...

Page 14

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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