ICM7170IBG Intersil, ICM7170IBG Datasheet - Page 10

• Manufacturer Part Number: ICM7170IBG
• Manufacturer: Intersil

Specifications of ICM7170IBG

• Bus Type: Multiplexed
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOIC W
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 24
• Mounting: Surface Mount
• Date Format: Binary
• Time Format: Binary
• Lead Free Status / RoHS Status: Not Compliant

The new load configuration (Figure 6) allows these two
conditions to be met independently. The two load capacitors,
C1 and C2, provide a fixed load to the oscillator and crystal.
C3 adjusts the frequency that the circuit resonates at by
reducing the effective value of the crystal's motional
capacitance, C0. This minute adjustment does not
appreciably change the load of the overall system, therefore,
stability is no longer affected by tuning. Typical values for
these capacitors are shown in Table 5. C1 and C2 must
always be greater than twice the crystal’s recommended load
capacitance in order for C3 to be able to trim the frequency.
Some experimentation may be necessary to determine the
ideal values of C1 and C2 for a particular crystal.
This three capacitor tuning method will be more stable than
the original design and is mandatory for 32kHz tuning fork
crystals: without it they may leap into an overtone mode
when power is initially applied.
The original two-capacitor circuit (Figure 8) will continue to
work as well as it always has, and may continue to be used
in applications where cost or space is a critical
consideration. It is also easier to tune to frequency since one
end of the trimmer capacitor is fixed at the AC ground of the
circuit (V
between the adjustment tool and the trimmer capacitor. Note
that in both configurations the load capacitors are connected
between the oscillator pins and V
AC ground.
Layout: Due to the extremely low current (and therefore high
impedance) design of the ICM7170s oscillator, special
attention must be given to the layout of this section. Stray
capacitance should be minimized. Keep the oscillator traces
FREQUENCY
FIGURE 8. ORIGINAL OSCILLATOR CONFIGURATION
CRYSTAL
OSC IN
32kHz
TABLE 5. TYPICAL LOAD CAPACITOR VALUES
1MHz
2MHz
4MHz
DD
), minimizing the disturbance cause by contact
10
C1
ICM7170
V
X1
DD
LOAD CAPS
OSC OUT
(C1, C2)
33pF
33pF
25pF
22pF
C2
10
DD
9
- do not use V
V
DD
23
TRIMMER CAP
C1 ≈ 2 x LOAD
C2 ≈ 5pF - 35pF
5 - 100pF
5 - 50pF
5 - 50pF
5 - 50pF
(C3)
SS
as an
ICM7170
on a single layer of the PCB. Avoid putting a ground plane
above or below this layer. The traces between the crystal,
the capacitors, and the ICM7170 OSC pins should be as
short as possible. Completely surround the oscillator
components with a thick trace of V
with any digital signals. The final assembly must be free from
contaminants such as solder flux, moisture, or any other
potential sources of leakage. A good solder mask will help
keep the traces free of moisture and contamination over
time.
Oscillator Tuning
Trimming the oscillator should be done indirectly. Direct
monitoring of the oscillator frequency by probing OSC IN or
OSC OUT is not accurate due to the capacitive loading of
most probes. One way to accurately trim the ICM7170 is by
turning on the 1 second periodic interrupt and trimming the
oscillator until the interrupt period is exactly one second.
This can be done as follows:
Application Notes
Digital Input Termination During Backup
To ensure low current drain during battery backup operation,
none of the digital inputs to the ICM7170 should be allowed
to float. This keeps the input logic gates out of their transition
region, and prevents crossover current from flowing which
will shorten battery life. The address, data, CS, and ALE pins
should be pulled to either V
inputs should be pulled to V
the internal battery switchover circuit is used or not.
IBM/PC Evaluation Circuit
Figure 9 shows the schematic of a board that has been
designed to plug into an IBM PC/XT (Note 1) or compatible
computer. In this example CS is permanently tied low and
access to the chip is controlled by the RD and WR pins.
These signals are generated by U1, which gates the IBM’s
lOR and lOW with a device select signal from U3, which is
1.Turn on the system. Write a 00H to the Interrupt Mask Register
2. Set the Command Register (location 11H) for the appropriate
3. Write a 08H to the Interrupt Mask Register to turn on the 1s
4. Write an interrupt handler to read the Interrupt Status Register
5. Connect a precision period counter capable of measuring 1s
6. Adjust C3 (C2 for the two-capacitor load configuration) for an
(location 10H) to clear all interrupts.
crystal frequency, set the Interrupt Enable and Run/Stop bits to
1, and set the Test bit to 0.
interrupt.
after every interrupt. This resets the interrupt and allows it to be
set again. A software loop that reads the Interrupt Status
Register several times each second will accomplish this also.
within the accuracy desired to the interrupt output. If the interrupt
is configured as active low, trigger on the falling edge. If the
interrupt is active high, trigger on the rising edge. Be sure to
measure the period between when the transistor turns ON, and
when the transistor turns ON a second later.
interrupt period of exactly 1.000000 seconds.
DD
DD
. This is necessary whether
or V
DD
SS
to minimize coupling
, and the RD and WR