PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 8

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PIC18F86J50T-I/PT

Manufacturer Part Number
PIC18F86J50T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets

Specifications of PIC18F86J50T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
I2C, MSSP, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
65
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
PIC18F86J50T-I/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F86J50T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F87J50 FAMILY
5. Module: Section 19.3 “SPI Mode” and
DS80481A-page 8
Note:
In Section 19.3 “SPI Mode” on page 231 and
Section 19.4 “I
following note is added to describe the procedure
to disable the MSSP module:
Disabling the MSSP module by clearing
the SSPEN bit (SSPxCON1<5>) may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
Section 19.4 “I
2
C™ Mode” on page 241, the
2
C™ Mode”
6. Module: Figure 19-10: I
On page 252, the figure is replaced with the new
timing diagram provided in Figure 19-10.
Timing (Transmission, 7-Bit
Address)
© 2009 Microchip Technology Inc.
2
C™ Slave Mode

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