CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 26

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
CY7C9689A REFCLK Input Switching Characteristics
CY7C9689A Receiver Switching Characteristics
Notes
f
t
t
t
t
t
t
t
t
21. When configured for synchronous operation with the FIFOs bypassed (FIFOBYP is LOW), if RANGESEL is HIGH the SPDSEL input is ignored and operation is
22. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
23. The PECL switching threshold is the midpoint between the PECL− V
24. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by the absolute difference of
25. Receiver UI (Unit Interval) is calculated as 1/(f
26. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
27. The specification is sum of 25% Duty Cycle Distortion (DCD), 10% Data Dependant Jitter (DDJ), 15% Random Jitter (RJ).
28. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
REF
REFCLK
REFH
REFL
REFRX
B
SA
EFW
IN_J
Parameter
[23]
Parameter
forced to the 100–200 MBaud range.
within ±0.04% of the transmitter PLL reference (REFCLK) frequency, necessitating a ±200-PPM crystal.
the left and right edge shifts (|t
of the remote transmitter if data is being received. In an operating link this is equivalent to N * t
ratios (2X or 4X, as selected by SPDSEL and RANGESEL), the numerator is multiplied by 2 or 4 respectively.
over the operating range, input jitter < 50% Dj.
REFCLK Clock Frequency—50 to 100 MBaud,
10-bit Mode, REFCLK = 2x Character Rate
REFCLK Clock Frequency—50 to 100 MBaud,
8-bit Mode, REFCLK = 2x Character Rate
REFCLK Clock Frequency—50 to 100 MBaud,
10-bit Mode, REFCLK = 4x Character Rate
REFCLK Clock Frequency—50 to 100 MBaud,
8-bit Mode, REFCLK = 4x Character Rate
REFCLK Clock Frequency—100 to 200 MBaud,
10-bit Mode, REFCLK = Character Rate
REFCLK Clock Frequency—100 to 200 MBaud,
8-bit Mode, REFCLK = Character Rate
REFCLK Clock Frequency—100 to 200 MBaud,
10-bit Mode, REFCLK = 2x Character Rate
REFCLK Clock Frequency—100 to 200 MBaud,
8-bit Mode, REFCLK = 2x Character Rate
REFCLK Period
REFCLK HIGH Time
REFCLK LOW Time
REFCLK Frequency Referenced to Received Clock Period
Bit Time
Static Alignment
Error Free Window
IN± Peak-to-Peak Input Jitter Tolerance
SH_L
– t
Description
[16, 24]
SH_R
[16, 25, 26]
|) of one bit until a character error occurs.
REF
*N) when operated in 8-bit mode (N = 10) and 10-bit mode (N = 12) if no data is being received, or 1/(f
Description
[16, 25, 27, 28]
OH
, and V
Over the Operating Range
SPDSEL RANGESEL BYTE8/10
OL
specification (approximately V
0
0
0
0
1
1
1
1
Over the Operating Range
[22]
Conditions
B
when REFCLK = 1X the character rate. An alternate multiply
1
1
[18]
[18]
0
0
0
0
1
1
DD
− 1.33V).
0
1
0
1
0
1
0
1
Min.
20.0
0.65
16.67
16.67
−0.04
Min.
8.33
8.33
6.5
6.5
10
20
10
20
25
CY7C9689A
Max.
600
5.0
0.5
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16.67
16.67
+0.04
Max.
33.3
33.3
120
20
40
20
40
Unit
REF
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ns
ps
UI
UI
ns
ns
ns
%
*N)
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