CY7C9689A-AC Cypress Semiconductor Corp, CY7C9689A-AC Datasheet - Page 10

• Manufacturer Part Number: CY7C9689A-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AC

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Pin Descriptions
71
12
75
74
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28
Control Signals
Pin
CE
REFCLK
SPDSEL
RANGESEL
RESET
FIFOBYP
Name
(continued)
TTL input sampled on
TXCLK↑, RXCLK↑, or
REFCLK↑
TTL clock input
Static control input
TTL levels
Normally wired HIGH
or LOW
Static control input
TTL levels
Normally wired HIGH
or LOW
Asynchronous
TTL input
Static control input
TTL levels
Normally wired HIGH
or LOW
I/O Characteristics
Chip Enable Input. Active LOW.
When CE is asserted and sampled LOW by RXCLK, the Receive FIFO status
flags are driven to their active states. When this input is deasserted and sampled
by RXCLK, the Receive FIFO status flags are placed in a High-Z state.
When CE has been sampled LOW and RXEN changes from deasserted to
asserted and is sampled by RXCLK, the RXSC/D, RXDATA[7:0],
RXDATA[9:8]/RXCMD[2:3] and VLTN output drivers are enabled and go to their
driven levels. These pins remain driven until RXEN is sampled deasserted.
When the Transmit FIFO is enabled (FIFOBYP is HIGH), and CE is asserted
and sampled by TXCLK, the Transmit FIFO status flags are driven to their active
states. When this input is deasserted and sampled by TXCLK, the Transmit
FIFO status flags are placed in a High-Z state.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), and CE is asserted
and sampled by REFCLK, the Transmit FIFO status flags are driven to their
active states. When this input is deasserted and sampled by REFCLK, the
Transmit FIFO status flags are placed in a High-Z state.
When the Transmit FIFO is enabled (FIFOBYP is HIGH), CE has been sampled
LOW, and TXEN changes from deasserted to asserted and is sampled by
TXCLK,
TXCMD[1:0] inputs are sampled and passed to the Transmit FIFO. These inputs
are sampled on all consecutive TXCLK cycles until TXEN is sampled
deasserted.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), CE has been
sampled LOW, and TXEN changes from deasserted to asserted and is sampled
by REFCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and
TXCMD[1:0] inputs are sampled and passed to the encoder or serializer as
directed by other control inputs. These inputs are sampled on all consecutive
REFCLK cycles until TXEN is sampled deasserted.
PLL Frequency Reference Clock.
This clock input is used as the timing reference for the transmit and receive
PLLs. When the Transmit FIFO is bypassed (FIFOBYP is HIGH), REFCLK is
also used as the clock for the parallel transmit interface.
Speed Select.
Used to select from one of two operating serial rates for the CY7C9689A. When
SPDSEL is HIGH, the signaling rate is between 100 and 200 MBaud. When
LOW, the signaling rate is between 50 and 100 MBaud. Used in combination
with RANGESEL and BYTE8/10 to configure the VCO multipliers and dividers.
Range Select.
Selects the proper prescaler for the REFCLK input. If RANGESEL is LOW, the
REFCLK input is passed directly to the Transmit PLL clock multiplier. If
RANGESEL is HIGH, REFLCK is divided by two before being sent to the
Transmit PLL multiplier.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), with RANGESEL
HIGH or SPDSEL LOW, TXFULL toggles at half the REFCLK rate to provide a
character rate indication, and to show when data can be accepted.
Master Reset for Internal Logic.
Pulsed LOW for one or more REFCLK cycles.
FIFO Bypass Enable.
When asserted, the Transmit and Receive FIFOs are bypassed. In this mode
TXCLK is not used. Instead all transmit data must be synchronous to REFCLK.
Transmit FIFO status flags are synchronized to REFCLK. All received data is
synchronous to RXCLK output. Receive FIFO status flags are synchronized to
RXCLK (the recovered Receive PLL character clock).
When not asserted, the Transmit and Receive FIFOs are enabled. In this mode
all Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO
reads are synchronous to the RXCLK input.
the
TXSC/D,
TXDATA[7:0],
Signal Description
TXDATA[9:8]/RXCMD[2:3],
CY7C9689A
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