KSZ8041TL A3 TR Micrel Inc, KSZ8041TL A3 TR Datasheet - Page 25

• Manufacturer Part Number: KSZ8041TL A3 TR
• Manufacturer: Micrel Inc

Specifications of KSZ8041TL A3 TR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
MII Management (MIIM) Interface
The KSZ8041TL/FTL/MLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KSZ8041TL/FTL/MLL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
The following table shows the MII Management frame format for the KSZ8041TL/FTL/MLL.
Interrupt (INTRP)
INTRP (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041TL/FTL/MLL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and
are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register
1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
By default, the KSZ8041TL/FTL/MLL is configured to MII mode after it is power-up or reset with the following:
December 2009
x
x
x
x
x
x
x
x
x
Read
Write
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows a external controller
to communicate with one or more PHY devices. Each KSZ8041TL/FTL/MLL device is assigned a unique PHY
address between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041TL/FTL/MLL device supports the
broadcast PHY address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a
single KSZ8041TL/FTL/MLL device, or write to multiple KSZ8041TL/FTL/MLL devices simultaneously.
A set of 16-bit MDIO registers. Register [0:6] are required, and their functions are defined per the IEEE 802.3
Specification. The additional registers are provided for expanded functionality.
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
A 25MHz crystal connected to XI, XO (pins 15, 14), or an external 25MHz clock source (oscillator) connected to
XI.
CONFIGURATION[2:0] (pins 27, 41, 40) set to ‘000’ (default setting).
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Read/Write
OP Code
10
01
Table 1. MII Management Frame Format
PHY
Address
Bits [4:0]
00AAA
00AAA
25
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Z0
10
Data
Bits [15:0]
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
KSZ8041TL/FTL/MLL
M9999-120909-1.2
Idle
Z
Z