KSZ8041TL A3 TR Micrel Inc, KSZ8041TL A3 TR Datasheet - Page 16

• Manufacturer Part Number: KSZ8041TL A3 TR
• Manufacturer: Micrel Inc

Specifications of KSZ8041TL A3 TR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
Note:
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE mode, or is not configured with an incorrect PHY Address.
December 2009
(KSZ8041FTL)
(KSZ8041TL)
Pin Number
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
23
42
42
Pin Name
NWAYEN
NWAYEN
DUPLEX
Type
Ipu/O
Ipu/O
Ipu/O
(1)
Pin Function
DUPLEX mode
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
Nway Auto-Negotiation Enable
During power-up / reset, this pin value is latched into register 0h bit 12.
If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable.
During power-up / reset, this pin value is latched into register 0h bit 12.
If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-
Negotiation.
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
16
KSZ8041TL/FTL/MLL
M9999-120909-1.2