WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet - Page 202

• Manufacturer Part Number: WBLXT9785HC.D0-865113
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HC.D0-865113

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 95
Cortina Systems
Interrupt Enable Register (Address 18, Hex 12)
®
1. R/W = Read/Write
2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = “11” and in
3. SFD Frame Alignment is applicable to SMII and SS-SMII only.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states
5. Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
12:9
Bit
13
RMII mode, Registers bits 18.15:14 = “11” or “10” cannot be used because the minimum Inter Gap Packet
becomes less than specified in the *IEEE 802.3 specification.
as the pin(s) are latched at startup or hardware reset
FIFO Depth Considerations , on page
8
7
6
5
4
3
2
1
0
Name
SFD Frame
Alignment
(RxDV asserts
with CRS when
enabled)
Reserved
CNTRMSK
ANMSK
SPEEDMSK
DUPLEXMSK
LINKMSK
ISOLMSK
Reserved
INTEN
TINT
3
Description
10 Mbps
100 Mbps
Mask for Counter Full
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Auto-Negotiate Complete
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Isolate Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
0 = Disable interrupts on this port
1 = Enable interrupts on this port
0 = Normal operation
1 = Test force interrupt on MDINT_L
Write as 0, ignore on Read
Write as 0, ignore on Read
50).
When Register bit 16.5 = 1, preamble is
not suppressed.
When Register bit 16.5 = 0, SFD is always
aligned, and preamble is suppressed.
When enabled, all but one byte of
preamble is suppressed.
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
7.0 Register Definitions
Type
Table 17, Receive
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Page 202
Default
0000
0
0
0
0
0
0
0
0
0
0
0