WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 80

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
3.4.2
Table 24
Cortina Systems
Signal Descriptions – RMII, SMII, and SS-SMII Configurations
RMII Signal Descriptions – BGA23 (Sheet 1 of 3)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID
3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W
BGA23
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
B13,
D13,
E14,
A14,
C14,
A11,
B11,
E12
C10
D11
A16
C16
D16
C3,
D8,
C6,
E6,
E2,
E3,
B2,
A7,
D4
Designation
F4
B5
A4
A6
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
Power-Down modes and during H/W reset.
Ball/Pin
PQFP
203
204
202
44
61
62
52
53
42
43
34
35
22
23
13
14
60
51
41
33
21
12
6
4
5
3
TxData0_0
TxData0_1
TxData1_0
TxData1_1
TxData2_0
TxData2_1
TxData3_0
TxData3_1
TxData4_0
TxData4_1
TxData5_0
TxData5_1
TxData6_0
TxData6_1
TxData7_0
TxData7_1
REFCLK0
REFCLK1
Symbol
TxEN0
TxEN1
TxEN2
TxEN3
TxEN4
TxEN5
TxEN6
TxEN7
Type
I, ID
I, ID
I, ID
I, ID
I, ID
I, ID
I, ID
I, ID
I, ID
I
1
Signal Description
Reference Clock.
50 MHz RMII reference clock is always required. RMII
inputs are sampled on the rising edge of REFCLK,
RMII outputs are sourced on the falling edge.
Transmit Data - Port 0.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 0 are clocked in synchronously to REFCLK.
Transmit Data - Port 1.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 1 are clocked in synchronously to REFCLK
Transmit Data - Port 2.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 2 are clocked in synchronously to REFCLK.
Transmit Data - Port 3.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 3 are clocked in synchronously to REFCLK.
Transmit Data - Port 4.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 4 are clocked in synchronously to REFCLK.
Transmit Data - Port 5.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 5 are clocked in synchronously to REFCLK.
Transmit Data - Port 6.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 6 are clocked in synchronously to REFCLK.
Transmit Data - Port 7.
Inputs containing 2-bit parallel di-bits to be transmitted
from port 7 are clocked in synchronously to REFCLK.
Transmit Enable - Ports 0-7.
Active High input enables respective port transmitter.
This signal must be synchronous to the REFCLK.
3.4 BGA23 Signal Descriptions
2,3
Page 80