WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 16

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Cortina Systems
Page
Page
200
201
204
205
207
207
209
211
212
214
215
216
227
109
110
112
112
114
129
131
133
111
49
70
1
Description
Modified Table 83 “Control Register (Address 0)”.
Modified Table 84 “Status Register (Address 1)”.
Modified Table 87 “Auto-Negotiation Advertisement Register (Address 4)”.
Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address 5)”.
Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register (Address 8)”.
Modified Table 92 “Port Configuration Register (Address 16, Hex 10)”.
Modified Table 93 “Quick Status Register (Address 17, Hex 11)”.
Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
Modified Table 95 “Interrupt Status Register (Address 19, Hex 13)”. Changed all references of RO/SC to R/LH.
Modified Table 97 “Receive Error Count Register (Address 21, Hex 15)”.
Modified Table 98 “RMII Out-of-Band Signaling Register (Address 25, Hex 19)”. Added note to Register bit 25.0.
Modified Table 99 “Trim Enable Register (Address 27, Hex 1B)”.
Modified Table 103 “Product Information”.
Description
Added bullet to Product Features
Modified Table 12 “Cortina Systems
FIFOSEL1 and FIFOSEL0)
Added Section 2.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode”
Modified Figure 38 “Recommended Cortina Systems
Circuitry”
Added Figure 39 “Recommended Cortina Systems
Circuitry”
Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”
Modified Table 28 “Absolute Maximum Ratings”
Modified Table 29 “Operating Conditions”
Modified Table 31 “Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)”(Output low voltage SD pins -
Max)
Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX Receive Timing
Parameters”
Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX Receive Timing
Parameters”
Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive Timing
Parameters”
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Revision Number: 006 (INTERNAL RELEASE)
Revision Date: June 10, 2003
Revision Date: January 2002
®
Revision Number: 005
LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added
®
LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
®
LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface
Revision History
Page 16