WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 3

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Cortina Systems
4.4
4.5
4.6
4.7
4.8
4.9
4.3.9
4.3.10 Global Hardware Control Interface ......................................................................121
4.3.11 FIFO Initial Fill Values..........................................................................................121
Operating Requirements...................................................................................................122
4.4.1
4.4.2
Initialization .......................................................................................................................123
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
Link Establishment............................................................................................................126
4.6.1
Serial MII Operation ..........................................................................................................128
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
RMII Operation .................................................................................................................137
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
100 Mbps Operation .........................................................................................................141
4.9.1
4.9.2
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
MII Interrupts........................................................................................................120
Power Requirements ...........................................................................................122
Clock/SYNC Requirements..................................................................................122
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
4.4.2.5
MDIO Control Mode .............................................................................................123
Hardware Control Mode.......................................................................................123
Power-Down Mode ..............................................................................................124
4.5.3.1
4.5.3.2
Reset ...................................................................................................................125
Hardware Configuration Settings .........................................................................126
Auto-Negotiation ..................................................................................................126
4.6.1.1
4.6.1.2
4.6.1.3
4.6.1.4
4.6.1.5
4.6.1.6
SMII Reference Clock ..........................................................................................132
TxSYNC Pulse (SMII/SS-SMII)............................................................................132
Transmit Data Stream..........................................................................................132
4.7.3.1
4.7.3.2
Receive Data Stream...........................................................................................133
4.7.4.1
4.7.4.2
4.7.4.3
4.7.4.4
Collision ...............................................................................................................133
Source Synchronous-Serial Media Independent Interface ..................................134
RMII Reference Clock..........................................................................................137
Transmit Enable...................................................................................................138
Carrier Sense & Data Valid..................................................................................138
Receive Error .......................................................................................................138
Out-of-Band Signaling .........................................................................................138
100BASE-X Network Operations .........................................................................141
100BASE-X Protocol Sublayer Operations..........................................................141
4.9.2.1
Reference Clock ..................................................................................122
TxCLK Signal (SS-SMII only)...............................................................122
TxSYNC Signal (SMII/SS-SMII) ...........................................................122
RxSYNC Signal (SS-SMII only) ...........................................................122
RxCLK Signal (SS-SMII Only) .............................................................123
Global (Hardware) Power Down ..........................................................125
Port (Software) Power Down ...............................................................125
Base Page Exchange ..........................................................................126
Manual Next Page Exchange ..............................................................126
Controlling Auto-Negotiation ................................................................127
Link Criteria..........................................................................................127
Parallel Detection.................................................................................127
Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode.........................................................................................128
Transmit Enable...................................................................................132
Transmit Error ......................................................................................132
Carrier Sense.......................................................................................133
Receive Data Valid ..............................................................................133
Receive Error .......................................................................................133
Receive Status Encoding.....................................................................133
PCS Sublayer ......................................................................................141
Contents
Page 3