LAN9215-MT Standard Microsystems (SMSC), LAN9215-MT Datasheet - Page 21

• Manufacturer Part Number: LAN9215-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9215-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9215
Transmit Data [3:0]
Reference Ground
Receive Data[3:0]
Reference Power
Transmit Enable
Collision Detect:
Transmit Clock:
Receive Clock
Receive Error
Carrier Sense
Receive Data
PLL Ground
PLL Power
Ground
NAME
NAME
Valid:
Note 2.1
Please refer to the SMSC application note ”AN14.9 - “Migrating from LAN9115 to the
LAN9215” for additional details.
VDD_REF
VSS_REF
VDD_PLL
VSS_PLL
SYMBOL
SYMBOL
RXD[3:0]
TXD[3:0]
RX_CLK
TX_CLK
TX_EN
RX_ER
RX_DV
GND
COL
CRS
Table 2.5 System and Power Signals (continued)
Table 2.6 MII Interface Signals
BUFFER
BUFFER
Note 2.2
TYPE
TYPE
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
(PD)
O8
O8
P
P
P
P
P
I
I
I
I
I
I
I
DATASHEET
21
PINS
NUM
NUM
PINS
12
1
1
1
1
1
4
1
1
1
1
1
1
1
GND for the PLL
Connected to 3.3v power and used as the
+1.8V Power from the internal PLL regulator.
This pin must be connected to a 10uF capacitor
(<2 Ohm ESR), in parallel with a 0.01uF
capacitor to ground. This pin must not be used
to supply power to other external devices. See
Note
(100-TQFP Package Only)
reference voltage for the internal PLL
Ground for internal PLL reference voltage
(100-TQFP Package Only)
Common Ground
(100-LFBGA Package Only)
Transmit Clock: 25MHz in 100Base-TX mode.
2.5MHz in 10Base-T mode.
Transmit Data 3-0: Data bits that are accepted
by the PHY for transmission.
When the internal PHY is selected, these
signals are driven low (0).
Transmit Enable: Indicates that valid data is
presented on the TXD[3:0] signals, for
transmission.
When the internal PHY is selected, this signal
is driven low (0).
Receive Clock: 25MHz in 100Base-TX mode.
2.5MHz in 10Base-T mode.
Receive Error: Asserted by the PHY to indicate
that an error was detected somewhere in the
frame presently being transferred from the PHY.
MII Collision Detect: Asserted by the PHY to
indicate detection of collision condition.
Receive Data 3-0: Data bits that are sent from
the PHY to the Ethernet MAC. See
Carrier Sense: Indicates detection of carrier.
Receive Data Valid: Indicates that recovered
and decoded data nibbles are being presented
by the PHY on RXD[3:0].
2.1.
DESCRIPTION
DESCRIPTION
Revision 2.7 (03-15-10)
Note
2.2.