MC33742SDW Freescale, MC33742SDW Datasheet - Page 48

MC33742SDW

Manufacturer Part Number
MC33742SDW
Description
Manufacturer
Freescale
Datasheet

Specifications of MC33742SDW

Data Rate
1000Kbps
Number Of Transceivers
1
Standard Supported
CAN 2.0
Operating Supply Voltage (max)
27V
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (min)
4.5V
Package Type
SOIC W
Supply Current
45mA
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
28
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC33742SDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MODE CONTROL REGISTER (MCR)
Table 15. Mode Control Register
Table 16. Mode Control Register Control Bits
Table 17. Mode Control Register Status Bits
48
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Notes
Notes
MCTR
Reset Condition (Write)
52.
53.
54.
55.
Tables 15
2
0
0
0
0
0
1
1
1
1
BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0V.
See
Watchdog ON or OFF depends on RCR bit D3.
Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be
previously set to logic [1].
VDDTEMP
Reset Value
MCTR
BATFAIL
WDRST
GFAIL
Name
$000b
1
0
0
1
1
1
0
0
1
1
MCR
Table 13
through
MCTR
0
0
1
0
1
1
0
1
0
1
page 47, for definitions of reset conditions
17
(53)
describes the various Mode Control Registers.
Enter/Exit Debug
Stop, Watchdog
Stop, Watchdog
33742S Mode
Sleep
Standby
Standby
OFF
R/W
Normal
Normal
ON
Mode
W
R
Stop
(54)
(54)
(55)
Logic
0
1
0
1
0
1
0
1
BATFAIL
To enter/exit Debug Mode, refer to detailed description in
Software Debug with the
No Watchdog running. Debug mode.
D3
(52)
VSUP was not below V
VSUP has been below V
No over-temperature pre-warning.
Temperature pre-warning on VDD regulator (bit latched).
No failure.
CAN Failure or HS over-temperature or V2 low.
No watchdog reset occurred.
Watchdog reset occurred.
POR, RESET
VDDTEMP
MCTR2
33742, page 34.
D2
0
BF
BF
.
.
Description
Description
POR, RESET
MCTR1
GFAIL
Analog Integrated Circuit Device Data
D1
0
Debug Mode: Hardware and
Freescale Semiconductor
POR, RESET
WDRST
MCTR0
D0
0

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